diff --git a/content/experiment-control/sinara-core.md b/content/experiment-control/sinara-core.md
index 74e1d03..334d1c3 100644
--- a/content/experiment-control/sinara-core.md
+++ b/content/experiment-control/sinara-core.md
@@ -30,9 +30,15 @@ One of the main devices in the Sinara family is the 1124 Carrier (codenamed Kasl
 
 {% end %}
 
+{% layout_text_img(src="images/kasli-soc@2x.png", popup="images/origin/kasli-soc.jpg", alt="", textleft=true, shadow=false) %}
 
+##### Sinara 1125 Carrier "Kasli-SoC"
 
-{% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", textleft=true, shadow=false) %}
+Based on a Zynq-7000 SoC, Kasli-SoC can execute kernels on a 1GHz CPU with a hardware FPU. This enables much heavier software computations to be performed on the core device with a low-latency path to the experiment. Network transfer rates are also greatly increased. Features are otherwise similar as Kasli's.
+
+{% end %}
+
+{% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", shadow=false) %}
 
 ##### Sinara 2118/2128/2138 8-channel isolated TTL cards
 
@@ -42,7 +48,7 @@ More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_b
 
 {% end %}
 
-{% layout_text_img(src="images/DIOMCX@2x.png", popup="images/origin/dio_mcx.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/DIOMCX@2x.png", popup="images/origin/dio_mcx.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 2238 16-channel non-isolated MCX TTL card
 
@@ -54,7 +60,7 @@ When higher densities or faster speeds are required, the Sinara 2238 MCX card is
 
 
 
-{% layout_text_img(src="images/LVDS@2x.png", popup="images/origin/dio_rj45.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/LVDS@2x.png", popup="images/origin/dio_rj45.jpg", alt="", shadow=false) %}
 
 
 ##### Sinara 2245 16-channel non-isolated LVDS RJ45 TTL card
@@ -68,7 +74,7 @@ Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually sel
 
 
 
-{% layout_text_img(src="images/Banker-TTL-1@2x.png", popup="images/origin/banker1.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Banker-TTL-1@2x.png", popup="images/origin/banker1.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 3128 TTL I/O expander "Banker"
 
@@ -84,7 +90,7 @@ Interfaces include:
 
 
 
-{% layout_text_img(src="images/Banker-TTL-2@2x.png", popup="images/origin/banker2.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Banker-TTL-2@2x.png", popup="images/origin/banker2.jpg", alt="", shadow=false) %}
 
 All outputs can be configured either as 3.3 or 5V. They can drive 50&#8486; load when set to 5V. FPGA can is configured from on-board FLASH. FLASH can be updated over I2C or with the on-board SPI connector.
 
@@ -105,7 +111,7 @@ There are several DIN-rail compatible modules for use with Banker. They are inte
 
 
 
-{% layout_text_img(src="images/Urukul-DDS@2x.png", popup="images/origin/urukul.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Urukul-DDS@2x.png", popup="images/origin/urukul.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 4410/4412 DDS "Urukul"
 
@@ -121,7 +127,7 @@ In regular mode, various DDS features are supported, including frequency, phase
 
 
 
-{% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", shadow=false) %}
 
 ##### Sinara 4456 synthesizer "Mirny"
 
@@ -145,7 +151,7 @@ Comparing Mirny to Urukul:
 
 
 
-{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 5432 DAC "Zotino"
 
@@ -171,7 +177,7 @@ Note that reaching this maximum hardware speed requires gateware acceleration; n
 
 
 
-{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", shadow=false) %}
 
 ##### Sinara 5108 Sampler
 
@@ -187,7 +193,7 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
 
 
 
-{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 6302 Grabber
 
@@ -201,7 +207,7 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
 
 
 
-{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", shadow=false) %}
 
 ##### Sinara 7210 Clocker
 
@@ -212,7 +218,7 @@ The Sinara 7210 is a low-noise clock distribution module that can be used to dis
 {% end %}
 
 
-{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 4624 AWG "Phaser"
 
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