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add zotino temperature data image (#61)

This patch adds a graph which shows that the temperature of Zotino can be stabilized using the Thermostat.
Co-authored-by: occheung <dc@m-labs.hk>
Co-committed-by: occheung <dc@m-labs.hk>
master
occheung 3 months ago
committed by sb10q
parent
commit
5a4f51504b
  1. 32
      content/experiment-control/sinara-core.md
  2. BIN
      static/images/origin/zotino-temp-eqm.png
  3. BIN
      static/images/origin/zotino-temp-var.png
  4. BIN
      static/images/zotino-temp-eqm.png
  5. BIN
      static/images/zotino-temp-var.png

32
content/experiment-control/sinara-core.md

@ -161,10 +161,30 @@ Zotino connects the 32 channels to both (a) a HD68 connector on its front panel
It is also possible to connect the Zotino using a HD68 cable to an external crate containing BNC-IDC or SMA-IDC cards.
The temperature of the DAC can be stabilized using the [Sinara 8451 Thermostat](../control-loops) to reduce output voltage drifts.
<a href="https://github.com/sinara-hw/Zotino/wiki" target="_blank" rel="noopener noreferrer">More information</a>
{% end %}
{% layout_text_img(src="images/zotino-temp-eqm.png", popup="images/origin/zotino-temp-eqm.png", alt="", shadow=false) %}
- The temperature of the Zotino DAC can be stabilized using the [Sinara 8451 Thermostat](../control-loops) to reduce output voltage drifts. A stable temperature can be re-established quickly after momentary disruption.
{% end %}
{% layout_text_img(src="images/zotino-temp-var.png", popup="images/origin/zotino-temp-var.png", alt="", textleft=true shadow=false) %}
- Zotino was placed on a table without protection from air currents, and an air conditioning unit generating disturbances nearby. The graph show its the temperature stability over 5 minutes while connected to the [Sinara Thermostat](../control-loops).
{% end %}
{% layout_text_img(src="images/side-min.png", shadow=false) %}
##### Sinara 5632 DAC "Fastino"
Fastino is a higher-speed version of Zotino. It also has 32 16-bit channels, but they all can be updated at 2Msps simultaneously (1Gb/s data).
@ -177,7 +197,7 @@ Note that reaching this maximum hardware speed requires gateware acceleration; n
{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", shadow=false) %}
{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", textleft=true, shadow=false) %}
##### Sinara 5108 Sampler
@ -193,7 +213,7 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", textleft=true, shadow=false) %}
{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", shadow=false) %}
##### Sinara 6302 Grabber
@ -207,7 +227,7 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", shadow=false) %}
{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", textleft=true, shadow=false) %}
##### Sinara 7210 Clocker
@ -218,7 +238,7 @@ The Sinara 7210 is a low-noise clock distribution module that can be used to dis
{% end %}
{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", textleft=true, shadow=false) %}
{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", shadow=false) %}
##### Sinara 4624 AWG "Phaser"

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static/images/origin/zotino-temp-eqm.png

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Width: 640  |  Height: 480  |  Size: 40 KiB

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static/images/origin/zotino-temp-var.png

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Width: 640  |  Height: 480  |  Size: 45 KiB

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static/images/zotino-temp-eqm.png

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Width: 631  |  Height: 468  |  Size: 31 KiB

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static/images/zotino-temp-var.png

After

Width: 631  |  Height: 468  |  Size: 31 KiB

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