diff --git a/content/experiment-control/sinara-core.md b/content/experiment-control/sinara-core.md
index 13b7940..bec1b5a 100644
--- a/content/experiment-control/sinara-core.md
+++ b/content/experiment-control/sinara-core.md
@@ -110,7 +110,31 @@ In regular mode, various DDS features are supported, including frequency, phase
 
 
 
-{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", textleft=true, shadow=false) %}
+
+##### Mirny PLL synthesizer card
+
+Mirny is a 4 channel wide-band PLL/VCO-based microwave frequency synthesiser.
+
+Like the Urukul DDS Synthesiser but with a VCO/PLL (ADF5356) as the synthesizer and options for frequency double/tripler and analog frontend mezzanines.
+
+Comparing Mirny to Urukul:
+
+- Much larger frequency range (53 MHz to >4 GHz vs. ~1 MHz to 500 MHz in the first Nyquist zone for Urukul). Up to 13.6 GHz when using the mezzanine.
+- Much higher frequency resolution.
+- Lower jitter and phase noise.
+- No linear high resolution output amplitude setting (c.f. AD9910 ASF).
+- No deterministic phase control, no coherent or absolute phase changes.
+- Large frequency changes are not "agile" (take a few ms) and do not have high timing resolution; small frequency changes (<10 kHz) can still be made rapidly.
+- RF switch changes or attenuator changes still benefit from high timing resolution through the EEM connector.
+
+<a href="https://github.com/sinara-hw/mirny/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+
+{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", shadow=false) %}
 
 ##### Zotino DAC card
 
@@ -126,7 +150,7 @@ It is also possible to connect the Zotino using a HD68 cable to an external crat
 
 
 
-{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sampler ADC card
 
@@ -142,7 +166,7 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
 
 
 
-{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", shadow=false) %}
 
 ##### Grabber camera interface
 
@@ -156,7 +180,7 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
 
 
 
-{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Clocker
 
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