52 lines
3.0 KiB
HTML
52 lines
3.0 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN"
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"http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
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<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
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<head>
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
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<title>M-Labs</title>
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<link rel="stylesheet" type="text/css" media="screen" href="style.css" />
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<link rel="icon" type="image/png" href="favicon.png" />
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</head>
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<body>
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<div id="logo"><img src="mlabs.svg">M-Labs</div>
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<div id="topmenu"><a href="mixxeo.html">Products</a> <a href="migen.html" class="selected">Technology</a> <a href="community.html">Community</a></div>
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<div id="leftmenu">
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<div id="leftmenutitle">Current</div>
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<ul>
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<li><a href="migen.html">Migen</a></li>
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<li><a href="msc.html">MiSoC</a></li>
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</ul>
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<div id="leftmenutitle">Legacy</div>
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<ul>
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<li><a href="mmsoc.html">Milkymist SoC</a></li>
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<li><a href="flickernoise.html">Flickernoise</a></li>
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</ul>
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</div>
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<div id="main">
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<div id="illus"><img src="wafers.jpg" alt="source: http://en.wikipedia.org/wiki/File:Wafer_2_Zoll_bis_8_Zoll_2.jpg"></div>
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<div id="title">Milkymist SoC</div>
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<p>The Milkymist SoC is at the core of our devices, implemented (so far) in a FPGA.</p>
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<p>The Milkymist <a href="http://en.wikipedia.org/wiki/System-on-chip">system-on-chip</a> uses the <a href="http://www.latticesemi.com/mico32">LatticeMico32</a> (LM32) core as a general purpose processor. It is a RISC 32-bit big endian CPU without a memory management unit (MMU). It is supported by the GCC compiler and can run <a href="http://www.rtems.com">RTEMS</a> and <a href="http://www.github.com/m-labs/linux-milkymist">uClinux</a>. There is also an <a href="https://github.com/m-labs/llvm-lm32">experimental back-end for LLVM</a> targeting this microprocessor.</p>
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<p>The LM32 microprocessor is assisted by a texture mapping unit and a programmable floating point VLIW coprocessor which are used by the Flickernoise video synthesis software. It is also surrounded by various peripheral cores to support every I/O device of the Milkymist One. The system-on-chip interconnect uses three bridged buses and mixes the Wishbone protocol with two custom protocols used for configuration registers and high performance DMA with the SDRAM.</p>
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<p>The architecture of the Milkymist system-on-chip is largely documented in the project founder's <a href="thesis/thesis.pdf">Master thesis report</a>. Most components of the system-on-chip, except the LatticeMico32 core, were custom developed and placed under the GNU GPL license.</p>
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<p>The QEMU emulator can be used to run and debug Milkymist SoC binaries on another computer.</p>
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<p>The SoC source distribution includes software libraries, the BIOS and the demonstration firmware, as well as test benches, LaTeX source for the documentation, build scripts, etc. The repository is hosted by GitHub and is available <a href="http://github.com/m-labs/milkymist">here</a>.</p>
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<p>Milkymist SoC is phased out in favor of the more powerful <a href="msc.html">MiSoC</a>.</p>
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</div>
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</body>
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</html>
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