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<h1 id="firstHeading" class="firstHeading">How to make a simple core for CSR bus</h1>
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<h3 id="siteSub">From Milkymist Wiki</h3>
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<div id="jump-to-nav">Jump to: <a href="index.php%3Ftitle=How_to_make_a_simple_core_for_CSR_bus.html#column-one">navigation</a>, <a href="index.php%3Ftitle=How_to_make_a_simple_core_for_CSR_bus.html#searchInput">search</a></div> <!-- start content -->
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<p>There is AVNET Spartan 3 Evaluation board that will be used for learning purposes, for this board there is fork of the Milkymist SoC with basic core functionality:
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(This example need to be ported to the Milkymist One Board)
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</p><p><b>Bus data is fixed at 32bits, remenber that !</b>
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</p>
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<pre>* LM32 Processor
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* CRS Bus
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* GPIO
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* UART
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* 16kbits On Chip Ram (2 KBytes)
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</pre>
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<p>In the milkymist-avnet directory you'll find two interesting folders:
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</p>
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<pre> cores <- source code of the system modules, you can find both rtl and doc folder for each one
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boards/avnet-sp3aevl <- related to the synthesis and core setup for specific board
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</pre>
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<p>Especially the file:
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</p>
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<pre> boards/avnet-sp3aevl/sources.mak
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</pre>
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<p>Points the included sources for the system, so you should consider add the new folders here, appending this:
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</p>
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<pre> COUNTER_SRC=$(wildcard $(CORES_DIR)/counter/rtl/*.v)
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</pre>
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<p>And fix last line as follow (note new directory is included):
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</p>
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<pre> CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC) $(COUNTER)
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</pre>
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<p>Before continue is good idea create a git branch so you can make sure what you change later using commits or even merging code with master branch, run thisy:
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</p>
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<pre> git checkout -b counter
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</pre>
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<p>Try make sure git know what changed and or new files added using:
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</p>
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<pre>git add <filename>
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</pre>
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<p>and when you selected all the files that would be part of the commit, that’s for the end all the tutorial when we got the new feature working :)
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</p><p>For the first edited file:
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</p>
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<pre>git add boards/avnet-sp3aevl/sources.mak
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</pre>
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<p>Remember do same for others.
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</p><p>This assume also you created the new directory.
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</p><p>Now create new folders:
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</p>
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<pre>mkdir cores/counter
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mkdir cores/counter/rtl
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mkdir cores/counter/doc
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</pre>
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<p>Then simply do:
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</p>
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<pre>git commit -m "commit message"
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</pre>
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<p>Now is time to start coding new core template, before i suggest keep in mind file:
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</p>
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<pre>boards/avnet-sp3aevl/rtl/system.v
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</pre>
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<p>Later we will need to add some lines there according to the core features.
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</p><p>New core file:
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</p>
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<pre> cores/customcore/rtl/counter.v
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</pre>
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<p>This core is intended to be simple as possible, mainly it is re-used code from the sysctl core for the GPIO input and CSR bus.
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</p><p>The counter have a single external clock input which is need to be synced with then Milkymist clock, to avoid <a href="http://www.eetimes.com/design/automotive-design/4018520/Understanding-Clock-Domain-Crossing-Issues" class="external text" title="http://www.eetimes.com/design/automotive-design/4018520/Understanding-Clock-Domain-Crossing-Issues" rel="nofollow">Clock Domain Crossing Issues</a>.
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</p><p>You can read more information in <a href="http://www.fpga4fun.com/CrossClockDomain.html" class="external text" title="http://www.fpga4fun.com/CrossClockDomain.html" rel="nofollow">fpg4fun</a> about how to implement a solution in verilog.
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</p><p><br />
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The counter code diff is here:
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</p>
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<pre><a href="images/2/23/Counter.diff" class="external free" title="http://milkymist.org/wiki/images/2/23/Counter.diff" rel="nofollow">http://milkymist.org/wiki/images/2/23/Counter.diff</a>
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</pre>
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<p><br />
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Check module in/out defintion
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</p><p>Input is defined:
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</p>
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<pre> input count_input
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</pre>
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<p>Now adding the counter core to the system editing:
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</p>
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<pre>boards/avnet-sp3aevl/rtl/system.v
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</pre>
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<p>This requires a bit more of editing, check code here:
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</p>
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<pre><a href="images/2/23/Counter.diff" class="external free" title="http://milkymist.org/wiki/images/2/23/Counter.diff" rel="nofollow">http://milkymist.org/wiki/images/2/23/Counter.diff</a>
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</pre>
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<p><br />
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Take look close to:
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</p>
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<pre>* GPIO
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* CSR Bus
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* WISHBONE to CSR bridge (For OR part check CSR bus topology)
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</pre>
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<p>The big part is from line 522, in wich:
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</p>
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<pre>* some parameters are filled with real values
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* core is linked to CSR
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* core input pin is linked to physical pin defined in the UCF file
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</pre>
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<p><br />
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Assign FPGA pins for external input editing file:
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</p>
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<pre> boards/avnet-sp3aevl/synthesis/common.ucf
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</pre>
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<p>With the new content:
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</p>
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<pre>NET "count(0)" LOC = E13 | IOSTANDARD = LVCMOS33;
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</pre>
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