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- M-Labs Limited |
+ M-Labs Limited |
Freenode #m-labs Developer mailing list GitHub: m-labs Twitter: @M_Labs_Ltd diff --git a/artiq.png b/artiq.png new file mode 100644 index 0000000..2ffd79e Binary files /dev/null and b/artiq.png differ diff --git a/ehsm_logo.png b/ehsm_logo.png deleted file mode 100644 index 8f7b3a1..0000000 Binary files a/ehsm_logo.png and /dev/null differ diff --git a/gateware.html b/gateware.html index 850a4eb..34fb8d7 100644 --- a/gateware.html +++ b/gateware.html @@ -30,7 +30,7 @@ Migen Migen is a Python-based tool that aims at automating further the VLSI design process. +Migen is a Python-based tool that automates further the VLSI design process. Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits, which represent the lion's share of today's logic designs. Counter-intuitive arithmetic rules result in steeper learning curves and provide a fertile ground for subtle bugs in designs. Finally, support for procedural generation of logic (metaprogramming) through "generate" statements is very limited and restricts the ways code can be made generic, reused and organized. @@ -85,7 +85,7 @@
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