add DSL FPGA workshop materials
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from migen.fhdl.std import *
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from mibuild.generic_platform import *
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from mibuild.platforms import papilio_pro
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from misoclib.uart import UARTRX
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# antenna pin description to place at one of the free GPIOs on the board
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_transmitter_io = [
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("antenna", 0, Pins("A:0"), IOStandard("LVTTL"))
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]
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# clock manager generating 300 MHz clock
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class ClockGen(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain(reset_less=True)
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clk300_unbuffered = Signal()
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self.specials += Instance("DCM_CLKGEN",
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p_CLKFXDV_DIVIDE=8, p_CLKFX_DIVIDE=8, p_CLKFX_MD_MAX=9.375, p_CLKFX_MULTIPLY=75,
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p_CLKIN_PERIOD=31.25, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="TRUE",
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i_CLKIN=platform.request("clk32"), o_CLKFX=clk300_unbuffered,
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i_FREEZEDCM=0, i_RST=0)
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self.specials += Instance("BUFG", i_I=clk300_unbuffered, o_O=self.cd_sys.clk)
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# Phase Accumulator module generating the target output frequencies
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# The magic happens here!
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class PhaseAccumulator(Module):
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def __init__(self, ??):
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self.out = Signal()
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## your code here
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class FMTransmitter(Module):
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def __init__(self, antenna, serial):
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# Clock generator module
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self.submodules.cg = ClockGen(platform)
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clk_freq = 300000000 # 300 MHz
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# UART receiver settings
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baud = 115200 # UART transmission speed
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# UART receiver
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self.submodules.uart = UARTRX(
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serial,
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baud*2**32//clk_freq)
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self.uart.source.payload.d.signed = True
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sample = Signal((8, True)) # the (signed) sound sample for you to transmit
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self.comb += sample.eq(self.uart.source.payload.d)
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# FM transmitter settings
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transmit_freq = ?? # carrier wave frequency in Hz
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phaseacc_nbits = ?? # counter width
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## your code here
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# some of the magic also happens here
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if __name__ == "__main__":
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platform = papilio_pro.Platform()
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platform.add_extension(_transmitter_io)
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antenna = platform.request("antenna")
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serial = platform.request("serial")
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top = FMTransmitter(antenna, serial)
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platform.build_cmdline(top)
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