From 8ff770080274a05439abef57655ccc4e9654ae40 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 14 May 2014 16:10:48 +0200
Subject: [PATCH] gateware: add mor1kx

---
 gateware.html | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gateware.html b/gateware.html
index 2f5c79b..850a4eb 100644
--- a/gateware.html
+++ b/gateware.html
@@ -61,7 +61,10 @@
 	<p>Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.</p>
 
 	<p><ul>
-	<li>LatticeMico32 CPU, modified to include an optional MMU (experimental).</li>
+	<li>CPU options:<ul>
+		<li>LatticeMico32, modified to include an optional MMU (experimental).</li>
+		<li><a href="https://github.com/openrisc/mor1kx">mor1kx</a>, a better OpenRISC implementation.</li>
+	</ul></li>
 	<li>High performance memory controller capable of issuing several SDRAM commands per FPGA cycle.</li>
 	<li>Supports SDR, DDR, LPDDR and DDR2.</li>
 	<li>Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.</li>