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@@ -61,7 +61,10 @@
 	<p>Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.</p>
 
 	<p><ul>
-	<li>LatticeMico32 CPU, modified to include an optional MMU (experimental).</li>
+	<li>CPU options:<ul>
+		<li>LatticeMico32, modified to include an optional MMU (experimental).</li>
+		<li><a href="https://github.com/openrisc/mor1kx">mor1kx</a>, a better OpenRISC implementation.</li>
+	</ul></li>
 	<li>High performance memory controller capable of issuing several SDRAM commands per FPGA cycle.</li>
 	<li>Supports SDR, DDR, LPDDR and DDR2.</li>
 	<li>Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.</li>