M-Labs/vexriscv-rust
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Fork of the riscv crate to support vexriscv
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Rust 66.9%
Shell 15.4%
Assembly 10.3%
PowerShell 7.4%
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Sean Cross b7befcf608
README: Obsolete
2020-03-18 23:36:30 +08:00
.github A unified contributing experience. 2018-08-12 08:59:12 +02:00
bin bin: update name of object file 2019-12-28 18:29:06 +08:00
ci Enable gcc caching 2019-03-17 17:24:07 +03:00
src register: add vexriscv-specific registers 2020-01-08 17:22:16 +08:00
.gitattributes vexriscv: clone from riscv crate 2019-12-28 18:12:31 +08:00
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.travis.yml Add MSRV policy 2019-03-17 17:29:48 +03:00
asm.S vexriscv: clone from riscv crate 2019-12-28 18:12:31 +08:00
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build.rs Implement asm functions 2019-01-23 01:29:54 +03:00
Cargo.toml cargo: bump version to 0.0.2 2020-01-08 17:23:05 +08:00
check-blobs.sh Implement asm functions 2019-01-23 01:29:54 +03:00
CODE_OF_CONDUCT.md Rename RISCV to RISC-V 2019-03-28 18:31:57 +01:00
LICENSE.md vexriscv: clone from riscv crate 2019-12-28 18:12:31 +08:00
README.md README: Obsolete 2020-03-18 23:36:30 +08:00

README.md

veriscv

Low level access to parts of the VexRiscv RISC-V processor

THIS PROJECT IS NOW OBSOLETE

You can access vexriscv-specific csrs in the riscv crate, under riscv::registers::vexriscv::*.