vexriscv-rust/Cargo.toml

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TOML

[package]
name = "riscv"
version = "0.1.3"
repository = "https://github.com/dvc94ch/riscv"
authors = ["David Craven <david@craven.ch>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISCV processors"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"
[dependencies]
bare-metal = "^0.1.1"
volatile-register = "^0.2.0"