51 lines
1.3 KiB
ArmAsm
51 lines
1.3 KiB
ArmAsm
#define REG_READ(name, offset) \
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.section .text.__read_ ## name; \
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.global __read_ ## name; \
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__read_ ## name: \
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csrrs a0, offset, x0; \
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ret
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#define REG_WRITE(name, offset) \
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.section .text.__write_ ## name; \
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.global __write_ ## name; \
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__write_ ## name: \
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csrrw x0, offset, a0; \
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ret
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#define REG_SET(name, offset) \
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.section .text.__set_ ## name; \
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.global __set_ ## name; \
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__set_ ## name: \
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csrrs x0, offset, a0; \
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ret
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#define REG_CLEAR(name, offset) \
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.section .text.__clear_ ## name; \
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.global __clear_ ## name; \
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__clear_ ## name: \
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csrrc x0, offset, a0; \
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ret
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#define REG_READ_WRITE(name, offset) REG_READ(name, offset); REG_WRITE(name, offset)
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#define REG_SET_CLEAR(name, offset) REG_SET(name, offset); REG_CLEAR(name, offset)
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#define RW(offset, name) REG_READ_WRITE(name, offset); REG_SET_CLEAR(name, offset)
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#define RO(offset, name) REG_READ(name, offset)
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#if __riscv_xlen == 32
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#define RW32(offset, name) RW(offset, name)
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#define RO32(offset, name) RO(offset, name)
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#else
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#define RW32(offset, name)
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#define RO32(offset, name)
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#endif
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// VexRiscv custom registers
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RW(0xBC0, vmim) // Machine IRQ Mask
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RO(0xFC0, vmip) // Machine IRQ Pending
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RW(0x9C0, vsim) // Supervisor IRQ Mask
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RO(0xDC0, vsip) // Supervisor IRQ Pending
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RO(0xCC0, vdci) // DCache Info
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