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47 Commits

Author SHA1 Message Date
Vadim Kaushan 31f4127702
Add PMP CSRs 2019-06-26 11:25:45 +03:00
Vadim Kaushan f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs 2019-06-26 00:51:37 +03:00
Vadim Kaushan 298a8b6f6e
Provide write() for mepc 2019-06-25 23:48:47 +03:00
Vadim Kaushan 7a8d3d1f6c
Implement mscratch and mtval registers 2019-06-25 23:48:27 +03:00
Vadim Kaushan 00367d4fd2
Add sections to the registers module 2019-06-25 23:34:47 +03:00
Vadim Kaushan ac2ac6756b
Derive useful traits for enums 2019-06-25 23:32:51 +03:00
Vadim Kaushan cf9008492a
Add marchid, mhartid and mimpid registers 2019-04-29 10:43:51 +02:00
Vadim Kaushan ca797a35d8
Fix Misa::has_extension() 2019-04-01 19:58:40 +03:00
Vadim Kaushan 5baba0cb32
Add write function for sstatus register 2019-03-28 18:56:49 +03:00
Vadim Kaushan 9bb3b5803c
Refactoring: use set_bits() in set_fs function 2019-03-28 17:59:07 +03:00
Vadim Kaushan 5ef90e3189
Fix set_spp and set_mpp functions 2019-03-28 17:57:40 +03:00
Vadim Kaushan 6a2bdbf38d
Refactoring 2019-03-18 18:25:16 +03:00
Vadim Kaushan 4fb81f4860
Add FS and XS fields of mstatus 2019-03-18 18:14:00 +03:00
bors[bot] 32eba6c1ea Merge #23 
23: Add fcsr register r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-03-17 18:47:24 +00:00
Vadim Kaushan 4ad2150a24
Add fcsr register 2019-03-17 19:06:29 +03:00
Vadim Kaushan 7d4919a67c
Add MSRV policy 2019-03-17 17:29:48 +03:00
Vadim Kaushan 799cdaf6d2
Fix docs 2019-03-17 17:28:05 +03:00
Vadim Kaushan 925c496949 Read composite CSRs as one 64-bit value 2019-03-01 17:46:35 +03:00
Vadim Kaushan b665adeb95 Refactoring: use get_bit() instead of shifts 2019-03-01 17:10:45 +03:00
Andy Russell 8cbb3878e5
move doc comments inside macro invocations 2019-02-19 15:19:02 -05:00
Vadim Kaushan 16fdb16730 Update docs 2019-01-24 17:20:23 +03:00
Vadim Kaushan ac1cba597a Fix RISC-V name 
https://riscv.org/risc-v-trademark-usage/
 2019-01-24 17:19:32 +03:00
Vadim Kaushan 061579f97e Call external functions when inline-asm is not set 2019-01-23 01:29:54 +03:00
Vadim Kaushan 41378757c0 Do not require const-fn and asm features 2019-01-23 01:29:54 +03:00
Vadim Kaushan 3652547073 Simplify #[cfg()] predicate expressions 2019-01-23 01:29:54 +03:00
Vadim Kaushan 52ad774fc1 Remove useless cfg_attr 2018-12-21 23:01:25 +01:00
Vadim Kaushan 921aa2bbec Refactoring: use new macros for M-mode CSRs 2018-12-21 22:49:23 +01:00
bors[bot] 8bffbd7291 Merge #12 #14 
12: Add some S-Mode CSRs r=dvc94ch a=wangrunji0408

Add these S-Mode CSRs:
- `sstatus`
- `stvec`
- `sie`
- `sip`
- `scause`
- `stval`
- `sscratch`
- `sepc`
- `satp`

as well as:
- `time`
- `timeh`

and S-Mode instructions:
- `sfence.vma`

Most of the code have been tested in the [RustOS](https://github.com/wangrunji0408/RustOS) project.

14: Remove ecall and *ret instructions from riscv::asm r=dvc94ch a=Disasm

* *ret instructions should not be used directly in Rust code, they should be used in handlers, written in asm ([example](273f0d4f70/src/lib.rs (L294-L340))).
* ecall instruction should be wrapped into something like syscall(), which should be declared in another platform-specific crate.

Co-authored-by: WangRunji <wangrunji0408@163.com>
Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2018-12-18 22:25:29 +00:00
Vadim Kaushan b790a0e92a Replace no-op with unimplemented!() 2018-12-19 00:01:36 +03:00
Vadim Kaushan 9550fe0687 Remove ecall and *ret instructions from riscv::asm 2018-12-18 23:58:50 +03:00
WangRunji 8776d30d3b add S-Mode registers 
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
 2018-11-09 22:42:46 +08:00
WangRunji 9dc7b40fdd impl sfence_vma & sfence_vma_all 2018-11-09 22:27:19 +08:00
bors[bot] 4e16dd85ed Merge #10 
10: these raw instructions are unsafe r=dvc94ch a=strake

`wfi` is safe, but the rest are not. Let's make them all unsafe until we have a better idea — the return types are wrong anyhow.


Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
 2018-08-19 17:02:05 +00:00
bors[bot] 591b7df808 Merge #9 
9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
 2018-08-19 11:12:24 +00:00
M Farkas-Dyck 8e0faa9182 these raw instructions are unsafe 2018-08-18 10:26:59 -08:00
M Farkas-Dyck 5a88960ee0 use `NonZeroUsize` where appropriate 2018-08-18 10:15:10 -08:00
M Farkas-Dyck ecc69bda00 mepc is word-size 2018-08-18 10:10:08 -08:00
Dan Callaghan 6769ac9262 fix target_arch conditionals to match "riscv32" and "riscv64" 
In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.

Include "riscv64" optimistically for future-proofing.
 2018-08-06 08:41:45 +10:00
Jakob Weisblat 8597f1c32d Fix typo in register/misa.rs 2018-04-02 08:17:23 +02:00
David Craven 45364b26a8
Add mepc register. 2018-03-30 12:14:27 +02:00
David Craven cd5200c5fa
Fix mstatus register value. 2018-03-29 15:37:49 +02:00
David Craven 7db0e71060
New api. 2018-03-27 20:17:44 +02:00
David Craven 179df42984
Remove inline(always). 2018-03-24 19:27:00 +01:00
David Craven 21bfaf49ae
mcause is read-only. 2017-11-21 09:52:15 +01:00
David Craven bb41b209a6
Read bits only once. 2017-11-20 14:14:01 +01:00
David Craven 467327cb15
Allow compiling on x86_64 for publishing. 2017-11-18 08:46:19 +01:00
David Craven e864581828
Initial commit. 2017-09-19 16:23:35 +02:00