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vexriscv-rust
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Fix mstatus register value.

This commit is contained in:
David Craven 2018-03-29 15:37:49 +02:00
parent 7db0e71060
commit cd5200c5fa
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GPG Key ID: 33B9E9FDE28D2C23
1 changed files with 2 additions and 2 deletions
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4
src/register/mstatus.rs
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@ -102,7 +102,7 @@ pub fn read() -> Mstatus {
unsafe fn set(bits: usize) {
match () {
#[cfg(target_arch = "riscv")]
() => asm!("csrrs x0, 0x305, $0" :: "r"(bits) :: "volatile"),
() => asm!("csrrs x0, 0x300, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))]
() => unimplemented!(),
}
@ -114,7 +114,7 @@ unsafe fn set(bits: usize) {
unsafe fn clear(bits: usize) {
match () {
#[cfg(target_arch = "riscv")]
() => asm!("csrrc x0, 0x305, $0" :: "r"(bits) :: "volatile"),
() => asm!("csrrc x0, 0x300, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))]
() => unimplemented!(),
}