M-Labs/vexriscv-rust
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Bump version and update url.

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David Craven 2018-08-12 07:50:11 +02:00
parent b03aae8850
commit be2a15f34e
1 changed files with 2 additions and 2 deletions
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Cargo.toml
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@ -1,7 +1,7 @@
[package] [package]
name = "riscv" name = "riscv"
version = "0.2.0" version = "0.3.0"
repository = "https://github.com/dvc94ch/riscv" repository = "https://github.com/rust-embedded/riscv"
authors = ["David Craven <david@craven.ch>"] authors = ["David Craven <david@craven.ch>"]
categories = ["embedded", "hardware-support", "no-std"] categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISCV processors" description = "Low level access to RISCV processors"