From b665adeb95b131e04d2d6f2e0a45b55398420498 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 1 Mar 2019 17:10:45 +0300
Subject: [PATCH] Refactoring: use get_bit() instead of shifts

---
 src/register/mie.rs | 20 +++++++++++---------
 src/register/mip.rs | 20 +++++++++++---------
 2 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/src/register/mie.rs b/src/register/mie.rs
index c55a52d..121a5b5 100644
--- a/src/register/mie.rs
+++ b/src/register/mie.rs
@@ -1,5 +1,7 @@
 //! mie register
 
+use bit_field::BitField;
+
 /// mie register
 #[derive(Clone, Copy, Debug)]
 pub struct Mie {
@@ -16,55 +18,55 @@ impl Mie {
     /// User Software Interrupt Enable
     #[inline]
     pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) == 1 << 0
+        self.bits.get_bit(0)
     }
 
     /// Supervisor Software Interrupt Enable
     #[inline]
     pub fn ssoft(&self) -> bool {
-        self.bits & (1 << 1) == 1 << 1
+        self.bits.get_bit(1)
     }
 
     /// Machine Software Interrupt Enable
     #[inline]
     pub fn msoft(&self) -> bool {
-        self.bits & (1 << 3) == 1 << 3
+        self.bits.get_bit(3)
     }
 
     /// User Timer Interrupt Enable
     #[inline]
     pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) == 1 << 4
+        self.bits.get_bit(4)
     }
 
     /// Supervisor Timer Interrupt Enable
     #[inline]
     pub fn stimer(&self) -> bool {
-        self.bits & (1 << 5) == 1 << 5
+        self.bits.get_bit(5)
     }
 
     /// Machine Timer Interrupt Enable
     #[inline]
     pub fn mtimer(&self) -> bool {
-        self.bits & (1 << 7) == 1 << 7
+        self.bits.get_bit(7)
     }
 
     /// User External Interrupt Enable
     #[inline]
     pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) == 1 << 8
+        self.bits.get_bit(8)
     }
 
     /// Supervisor External Interrupt Enable
     #[inline]
     pub fn sext(&self) -> bool {
-        self.bits & (1 << 9) == 1 << 9
+        self.bits.get_bit(9)
     }
 
     /// Machine External Interrupt Enable
     #[inline]
     pub fn mext(&self) -> bool {
-        self.bits & (1 << 11) == 1 << 11
+        self.bits.get_bit(11)
     }
 }
 
diff --git a/src/register/mip.rs b/src/register/mip.rs
index 076a019..6633088 100644
--- a/src/register/mip.rs
+++ b/src/register/mip.rs
@@ -1,5 +1,7 @@
 //! mip register
 
+use bit_field::BitField;
+
 /// mip register
 #[derive(Clone, Copy, Debug)]
 pub struct Mip {
@@ -16,55 +18,55 @@ impl Mip {
     /// User Software Interrupt Pending
     #[inline]
     pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) == 1 << 0
+        self.bits.get_bit(0)
     }
 
     /// Supervisor Software Interrupt Pending
     #[inline]
     pub fn ssoft(&self) -> bool {
-        self.bits & (1 << 1) == 1 << 1
+        self.bits.get_bit(1)
     }
 
     /// Machine Software Interrupt Pending
     #[inline]
     pub fn msoft(&self) -> bool {
-        self.bits & (1 << 3) == 1 << 3
+        self.bits.get_bit(3)
     }
 
     /// User Timer Interrupt Pending
     #[inline]
     pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) == 1 << 4
+        self.bits.get_bit(4)
     }
 
     /// Supervisor Timer Interrupt Pending
     #[inline]
     pub fn stimer(&self) -> bool {
-        self.bits & (1 << 5) == 1 << 5
+        self.bits.get_bit(5)
     }
 
     /// Machine Timer Interrupt Pending
     #[inline]
     pub fn mtimer(&self) -> bool {
-        self.bits & (1 << 7) == 1 << 7
+        self.bits.get_bit(7)
     }
 
     /// User External Interrupt Pending
     #[inline]
     pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) == 1 << 8
+        self.bits.get_bit(8)
     }
 
     /// Supervisor External Interrupt Pending
     #[inline]
     pub fn sext(&self) -> bool {
-        self.bits & (1 << 9) == 1 << 9
+        self.bits.get_bit(9)
     }
 
     /// Machine External Interrupt Pending
     #[inline]
     pub fn mext(&self) -> bool {
-        self.bits & (1 << 11) == 1 << 11
+        self.bits.get_bit(11)
     }
 }