diff --git a/README.md b/README.md
index 475c535..cec900a 100644
--- a/README.md
+++ b/README.md
@@ -1,88 +1,18 @@
+[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv)
+[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv)
+[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv)
+
 # `riscv`
 
 > Low level access to RISCV processors
 
-## Implemented Peripherals
-- [ ] plic
-- [ ] clint
+This project is developed and maintained by the [RISCV team][team].
 
-## Implemented privileged ASM instructions
-- [x] ecall
-- [x] ebreak
-- [x] uret
-- [x] sret
-- [x] mret
-- [x] wfi
-- [ ] sfence.vma
+## [Documentation](https://docs.rs/crate/riscv)
 
-## Implemented CSR's
+## License
 
-### User mode
-- [ ] ustatus
-- [ ] uie
-- [ ] utvec
-- [ ] uscratch
-- [ ] uepc
-- [ ] ucause
-- [ ] utval
-- [ ] uip
-- [ ] fflags
-- [ ] frm
-- [ ] fcsr
-- [ ] cycle
-- [ ] time
-- [ ] instret
-- [ ] hpmcounter[3-31]
-- [ ] cycleh
-- [ ] timeh
-- [ ] instreth
-- [ ] hpmcounter[3-31]h
-
-### Supervisor mode
-- [ ] sstatus
-- [ ] sedeleg
-- [ ] sideleg
-- [ ] sie
-- [ ] stvec
-- [ ] scounteren
-- [ ] sscratch
-- [ ] sepc
-- [ ] scause
-- [ ] stval
-- [ ] sip
-- [ ] satp
-
-### Machine mode
-- [x] mvendorid
-- [ ] marchid
-- [ ] mimpid
-- [ ] mhartid
-- [x] mstatus
-- [x] misa
-- [ ] medeleg
-- [ ] mideleg
-- [x] mie
-- [x] mtvec
-- [ ] mcounteren
-- [ ] mscratch
-- [x] mepc
-- [x] mcause
-- [ ] mtval
-- [x] mip
-- [ ] pmpcfg[0-3]
-- [ ] pmpaddr[0-15]
-- [x] mcycle
-- [x] minstret
-- [ ] mhpmcounter[3-31]
-- [x] mcycleh
-- [x] minstreth
-- [ ] mhpmcounter[3-31]h
-- [ ] mhpmevent[3-31]
-- [ ] tselect
-- [ ] tdata[1-3]
-
-# License
-Copyright 2017 David Craven
+Copyright 2018 [RISCV team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -95,3 +25,12 @@ INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
 THIS SOFTWARE.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [RISCV team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: CODE_OF_CONDUCT.md
+[team]: https://github.com/rust-embedded/wg#the-riscv-team