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fix target_arch conditionals to match "riscv32" and "riscv64" 

In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.

Include "riscv64" optimistically for future-proofing.
This commit is contained in:
Dan Callaghan 2018-08-05 12:37:47 +10:00
parent 87bcdd8bab
commit 6769ac9262
14 changed files with 45 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/asm.rs
View File

@ -5,11 +5,11 @@ macro_rules! instruction {
#[inline] #[inline]
pub fn $fnname() { pub fn $fnname() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => unsafe { () => unsafe {
asm!($asm :::: "volatile"); asm!($asm :::: "volatile");
}, },
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => {} () => {}
} }
} }

8
src/interrupt.rs
View File

@ -8,9 +8,9 @@ use register::mstatus;
#[inline] #[inline]
pub unsafe fn disable() { pub unsafe fn disable() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => mstatus::clear_mie(), () => mstatus::clear_mie(),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => {} () => {}
} }
} }
@ -23,9 +23,9 @@ pub unsafe fn disable() {
#[inline] #[inline]
pub unsafe fn enable() { pub unsafe fn enable() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => mstatus::set_mie(), () => mstatus::set_mie(),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => {} () => {}
} }
} }

4
src/register/mcause.rs
View File

@ -140,7 +140,7 @@ impl Mcause {
#[inline] #[inline]
pub fn read() -> Mcause { pub fn read() -> Mcause {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -148,7 +148,7 @@ pub fn read() -> Mcause {
} }
Mcause { bits: r } Mcause { bits: r }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/mcycle.rs
View File

@ -4,7 +4,7 @@
#[inline] #[inline]
pub fn read() -> usize { pub fn read() -> usize {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -12,7 +12,7 @@ pub fn read() -> usize {
} }
r r
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/mcycleh.rs
View File

@ -4,7 +4,7 @@
#[inline] #[inline]
pub fn read() -> usize { pub fn read() -> usize {
match () { match () {
#[cfg(all(target_arch = "riscv", target_pointer_width = "32"))] #[cfg(target_arch = "riscv32")]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -12,7 +12,7 @@ pub fn read() -> usize {
} }
r r
} }
#[cfg(any(not(target_arch = "riscv"), not(target_pointer_width = "32")))] #[cfg(not(target_arch = "riscv32"))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/mepc.rs
View File

@ -4,7 +4,7 @@
#[inline] #[inline]
pub fn read() -> u32 { pub fn read() -> u32 {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -12,7 +12,7 @@ pub fn read() -> u32 {
} }
r as u32 r as u32
}, },
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

16
src/register/mie.rs
View File

@ -72,7 +72,7 @@ impl Mie {
#[inline] #[inline]
pub fn read() -> Mie { pub fn read() -> Mie {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -80,31 +80,31 @@ pub fn read() -> Mie {
} }
Mie { bits: r } Mie { bits: r }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
/// Sets the CSR /// Sets the CSR
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))] #[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
#[inline] #[inline]
unsafe fn set(bits: usize) { unsafe fn set(bits: usize) {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => asm!("csrrs x0, 0x304, $0" :: "r"(bits) :: "volatile"), () => asm!("csrrs x0, 0x304, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
/// Clears the CSR /// Clears the CSR
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))] #[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
#[inline] #[inline]
unsafe fn clear(bits: usize) { unsafe fn clear(bits: usize) {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => asm!("csrrc x0, 0x304, $0" :: "r"(bits) :: "volatile"), () => asm!("csrrc x0, 0x304, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/minstret.rs
View File

@ -4,7 +4,7 @@
#[inline] #[inline]
pub fn read() -> usize { pub fn read() -> usize {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -12,7 +12,7 @@ pub fn read() -> usize {
} }
r r
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/minstreth.rs
View File

@ -4,7 +4,7 @@
#[inline] #[inline]
pub fn read() -> usize { pub fn read() -> usize {
match () { match () {
#[cfg(all(target_arch = "riscv", target_pointer_width = "32"))] #[cfg(target_arch = "riscv32")]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -12,7 +12,7 @@ pub fn read() -> usize {
} }
r r
}, },
#[cfg(any(not(target_arch = "riscv"), not(target_pointer_width = "32")))] #[cfg(not(target_arch = "riscv32"))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/mip.rs
View File

@ -72,7 +72,7 @@ impl Mip {
#[inline] #[inline]
pub fn read() -> Mip { pub fn read() -> Mip {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -80,7 +80,7 @@ pub fn read() -> Mip {
} }
Mip { bits: r } Mip { bits: r }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/misa.rs
View File

@ -49,7 +49,7 @@ impl Misa {
#[inline] #[inline]
pub fn read() -> Option<Misa> { pub fn read() -> Option<Misa> {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -63,7 +63,7 @@ pub fn read() -> Option<Misa> {
Some(Misa { bits: r }) Some(Misa { bits: r })
} }
}, },
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

16
src/register/mstatus.rs
View File

@ -83,7 +83,7 @@ impl Mstatus {
#[inline] #[inline]
pub fn read() -> Mstatus { pub fn read() -> Mstatus {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -91,31 +91,31 @@ pub fn read() -> Mstatus {
} }
Mstatus { bits: r } Mstatus { bits: r }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
/// Sets the CSR /// Sets the CSR
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))] #[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
#[inline] #[inline]
unsafe fn set(bits: usize) { unsafe fn set(bits: usize) {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => asm!("csrrs x0, 0x300, $0" :: "r"(bits) :: "volatile"), () => asm!("csrrs x0, 0x300, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
/// Clears the CSR /// Clears the CSR
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))] #[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
#[inline] #[inline]
unsafe fn clear(bits: usize) { unsafe fn clear(bits: usize) {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => asm!("csrrc x0, 0x300, $0" :: "r"(bits) :: "volatile"), () => asm!("csrrc x0, 0x300, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

10
src/register/mtvec.rs
View File

@ -38,7 +38,7 @@ impl Mtvec {
#[inline] #[inline]
pub fn read() -> Mtvec { pub fn read() -> Mtvec {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -46,20 +46,20 @@ pub fn read() -> Mtvec {
} }
Mtvec { bits: r } Mtvec { bits: r }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
/// Writes the CSR /// Writes the CSR
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))] #[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
#[inline] #[inline]
pub unsafe fn write(addr: usize, mode: TrapMode) { pub unsafe fn write(addr: usize, mode: TrapMode) {
let bits = addr + mode as usize; let bits = addr + mode as usize;
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => asm!("csrrw x0, 0x305, $0" :: "r"(bits) :: "volatile"), () => asm!("csrrw x0, 0x305, $0" :: "r"(bits) :: "volatile"),
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

4
src/register/mvendorid.rs
View File

@ -22,7 +22,7 @@ impl Mvendorid {
#[inline] #[inline]
pub fn read() -> Option<Mvendorid> { pub fn read() -> Option<Mvendorid> {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
() => { () => {
let r: usize; let r: usize;
unsafe { unsafe {
@ -36,7 +36,7 @@ pub fn read() -> Option<Mvendorid> {
Some(Mvendorid { bits: r }) Some(Mvendorid { bits: r })
} }
} }
#[cfg(not(target_arch = "riscv"))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),
} }
} }