From 4fb81f4860d67c432705e6039dabc2b1e7dc4fa0 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Mon, 18 Mar 2019 18:08:14 +0300 Subject: [PATCH 1/7] Add FS and XS fields of mstatus --- asm.S | 2 +- src/register/mstatus.rs | 64 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/asm.S b/asm.S index 89890be..d6d03fd 100644 --- a/asm.S +++ b/asm.S @@ -36,7 +36,7 @@ REG_SET_CLEAR(mie, 0x304) REG_READ(minstret, 0xB02) REG_READ(mip, 0x344) REG_READ(misa, 0x301) -REG_READ(mstatus, 0x300) +REG_READ_WRITE(mstatus, 0x300) REG_SET_CLEAR(mstatus, 0x300) REG_READ_WRITE(mtvec, 0x305) REG_READ(mvendorid, 0xF11) diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs index d60792d..667ef7b 100644 --- a/src/register/mstatus.rs +++ b/src/register/mstatus.rs @@ -1,12 +1,37 @@ //! mstatus register // TODO: Virtualization, Memory Privilege and Extension Context Fields +use bit_field::BitField; + /// mstatus register #[derive(Clone, Copy, Debug)] pub struct Mstatus { bits: usize, } +/// Additional extension state +pub enum XS { + /// All off + AllOff = 0, + + /// None dirty or clean, some on + NoneDirtyOrClean = 1, + + /// None dirty, some clean + NoneDirtySomeClean = 2, + + /// Some dirty + SomeDirty = 3, +} + +/// Floating-point extension state +pub enum FS { + Off = 0, + Initial = 1, + Clean = 2, + Dirty = 3, +} + /// Machine Previous Privilege Mode pub enum MPP { Machine = 3, @@ -76,10 +101,40 @@ impl Mstatus { _ => unreachable!(), } } + + /// Floating-point extension state + /// + /// Encodes the status of the floating-point unit, + /// including the CSR `fcsr` and floating-point data registers `f0–f31`. + #[inline] + pub fn fs(&self) -> FS { + match self.bits.get_bits(13..15) { + 0b00 => FS::Off, + 0b01 => FS::Initial, + 0b10 => FS::Clean, + 0b11 => FS::Dirty, + _ => unreachable!(), + } + } + + /// Additional extension state + /// + /// Encodes the status of additional user-mode extensions and associated state. + #[inline] + pub fn xs(&self) -> XS { + match self.bits.get_bits(15..17) { + 0b00 => XS::AllOff, + 0b01 => XS::NoneDirtyOrClean, + 0b10 => XS::NoneDirtySomeClean, + 0b11 => XS::SomeDirty, + _ => unreachable!(), + } + } } read_csr_as!(Mstatus, 0x300, __read_mstatus); +write_csr!(0x300, __write_mstatus); set!(0x300, __set_mstatus); clear!(0x300, __clear_mstatus); @@ -111,3 +166,12 @@ pub unsafe fn set_spp(spp: SPP) { pub unsafe fn set_mpp(mpp: MPP) { _set((mpp as usize) << 11); } + +/// Floating-point extension state +#[inline] +pub unsafe fn set_fs(fs: FS) { + let mut value = _read(); + value &= !(0b11 << 13); + value |= (fs as usize) << 13; + _write(value); +} From 6a2bdbf38de1e4c486ef08ac48d79782795d582d Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Mon, 18 Mar 2019 18:25:16 +0300 Subject: [PATCH 2/7] Refactoring --- src/register/mstatus.rs | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs index 667ef7b..16ea4e1 100644 --- a/src/register/mstatus.rs +++ b/src/register/mstatus.rs @@ -49,43 +49,43 @@ impl Mstatus { /// User Interrupt Enable #[inline] pub fn uie(&self) -> bool { - self.bits & (1 << 0) == 1 << 0 + self.bits.get_bit(0) } /// Supervisor Interrupt Enable #[inline] pub fn sie(&self) -> bool { - self.bits & (1 << 1) == 1 << 1 + self.bits.get_bit(1) } /// Machine Interrupt Enable #[inline] pub fn mie(&self) -> bool { - self.bits & (1 << 3) == 1 << 3 + self.bits.get_bit(3) } /// User Previous Interrupt Enable #[inline] pub fn upie(&self) -> bool { - self.bits & (1 << 4) == 1 << 4 + self.bits.get_bit(4) } /// Supervisor Previous Interrupt Enable #[inline] pub fn spie(&self) -> bool { - self.bits & (1 << 5) == 1 << 5 + self.bits.get_bit(5) } /// User Previous Interrupt Enable #[inline] pub fn mpie(&self) -> bool { - self.bits & (1 << 7) == 1 << 7 + self.bits.get_bit(7) } /// Supervisor Previous Privilege Mode #[inline] pub fn spp(&self) -> SPP { - match self.bits & (1 << 8) == (1 << 8) { + match self.bits.get_bit(8) { true => SPP::Supervisor, false => SPP::User, } @@ -94,7 +94,7 @@ impl Mstatus { /// Machine Previous Privilege Mode #[inline] pub fn mpp(&self) -> MPP { - match (self.bits & (0b11 << 11)) >> 11 { + match self.bits.get_bits(11..13) { 0b00 => MPP::User, 0b01 => MPP::Supervisor, 0b11 => MPP::Machine, @@ -141,26 +141,33 @@ clear!(0x300, __clear_mstatus); set_clear_csr!( /// User Interrupt Enable , set_uie, clear_uie, 1 << 0); + set_clear_csr!( /// Supervisor Interrupt Enable , set_sie, clear_sie, 1 << 1); + set_clear_csr!( /// Machine Interrupt Enable , set_mie, clear_mie, 1 << 3); + set_csr!( /// User Previous Interrupt Enable , set_upie, 1 << 4); + set_csr!( /// Supervisor Previous Interrupt Enable , set_spie, 1 << 5); + set_csr!( /// Machine Previous Interrupt Enable , set_mpie, 1 << 7); + /// Supervisor Previous Privilege Mode #[inline] pub unsafe fn set_spp(spp: SPP) { _set((spp as usize) << 8); } + /// Machine Previous Privilege Mode #[inline] pub unsafe fn set_mpp(mpp: MPP) { From 5ef90e31891019f6b046471ed03ef5cbd455aa2e Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Thu, 28 Mar 2019 17:42:38 +0300 Subject: [PATCH 3/7] Fix set_spp and set_mpp functions --- src/register/mstatus.rs | 9 +++++++-- src/register/sstatus.rs | 9 +++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs index 16ea4e1..e18f30c 100644 --- a/src/register/mstatus.rs +++ b/src/register/mstatus.rs @@ -165,13 +165,18 @@ set_csr!( /// Supervisor Previous Privilege Mode #[inline] pub unsafe fn set_spp(spp: SPP) { - _set((spp as usize) << 8); + match spp { + SPP::Supervisor => _set(1 << 8), + SPP::User => _clear(1 << 8), + } } /// Machine Previous Privilege Mode #[inline] pub unsafe fn set_mpp(mpp: MPP) { - _set((mpp as usize) << 11); + let mut value = _read(); + value.set_bits(11..13, mpp as usize); + _write(value); } /// Floating-point extension state diff --git a/src/register/sstatus.rs b/src/register/sstatus.rs index 7ae3d4e..b770030 100644 --- a/src/register/sstatus.rs +++ b/src/register/sstatus.rs @@ -131,12 +131,17 @@ set_clear_csr!( #[inline] #[cfg(riscv)] pub unsafe fn set_spp(spp: SPP) { - _set((spp as usize) << 8); + match spp { + SPP::Supervisor => _set(1 << 8), + SPP::User => _clear(1 << 8), + } } /// The status of the floating-point unit #[inline] #[cfg(riscv)] pub unsafe fn set_fs(fs: FS) { - _set((fs as usize) << 13); + let mut value = _read(); + value.set_bits(13..15, fs as usize); + _write(value); } From 9bb3b5803ce23ab78ce643b9200d6b09c9374f58 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Thu, 28 Mar 2019 17:59:07 +0300 Subject: [PATCH 4/7] Refactoring: use set_bits() in set_fs function --- src/register/mstatus.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs index e18f30c..3988097 100644 --- a/src/register/mstatus.rs +++ b/src/register/mstatus.rs @@ -183,7 +183,6 @@ pub unsafe fn set_mpp(mpp: MPP) { #[inline] pub unsafe fn set_fs(fs: FS) { let mut value = _read(); - value &= !(0b11 << 13); - value |= (fs as usize) << 13; + value.set_bits(13..15, fs as usize); _write(value); } From 5baba0cb32e8cd1936af9c5f4400c2736c88ea90 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Thu, 28 Mar 2019 18:56:49 +0300 Subject: [PATCH 5/7] Add write function for sstatus register --- asm.S | 2 +- src/register/sstatus.rs | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/asm.S b/asm.S index d6d03fd..1a83960 100644 --- a/asm.S +++ b/asm.S @@ -49,7 +49,7 @@ REG_READ(sie, 0x104) REG_SET_CLEAR(sie, 0x104) REG_READ(sip, 0x144) REG_READ_WRITE(sscratch, 0x140) -REG_READ(sstatus, 0x100) +REG_READ_WRITE(sstatus, 0x100) REG_SET_CLEAR(sstatus, 0x100) REG_READ(stval, 0x143) REG_READ_WRITE(stvec, 0x105) diff --git a/src/register/sstatus.rs b/src/register/sstatus.rs index b770030..ec4765a 100644 --- a/src/register/sstatus.rs +++ b/src/register/sstatus.rs @@ -105,6 +105,7 @@ impl Sstatus { } read_csr_as!(Sstatus, 0x100, __read_sstatus); +write_csr!(0x100, __write_sstatus); set!(0x100, __set_sstatus); clear!(0x100, __clear_sstatus); From 7112ef8af22f7a03f37059e0db114860302c99a7 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Thu, 28 Mar 2019 18:57:28 +0300 Subject: [PATCH 6/7] Regenerate blobs --- bin/riscv32imac-unknown-none-elf.a | Bin 6686 -> 6958 bytes bin/riscv32imc-unknown-none-elf.a | Bin 6686 -> 6958 bytes bin/riscv64gc-unknown-none-elf.a | Bin 7638 -> 7990 bytes bin/riscv64imac-unknown-none-elf.a | Bin 7638 -> 7990 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/bin/riscv32imac-unknown-none-elf.a b/bin/riscv32imac-unknown-none-elf.a index 2bb3df2d87b74c8b861770f61bbd46d157bd6a15..bf9a2065c1924dc8ed91fd1bebb4e0490467f0f9 100644 GIT binary patch delta 928 zcmchVJ7^S96o&shcgDDR=;W~z6B9Qvkh`wgjT_duDKw3R-MV!MkpvOn5`?u|LBT>q z;je6rtq59-BEe1&Em8(zAwEE`ijr7Zh4tuef+wxuf&ZKPojY@fduJXLo{Zm{s7@3I z>UF9aKn}38|1&54?Pc8`fO=Rm(X#Hw_j&=vTk<%7i&0#q zU44OW8MR>D_^kz7J)^4r>u9zE6E<4H&mi3X#J@6e7PjznaD|_TC;S4&h4;f3ezA@T z(MV!m_y8UVAHj79rccqrycc$ZZn&7kEziL)1o&_mwqry z6iYa&Oa0VBNB9LM08oG?e{bnDRxerELCPKDM^0)^m%J*WQ#XLxAg diff --git a/bin/riscv32imc-unknown-none-elf.a b/bin/riscv32imc-unknown-none-elf.a index 2bb3df2d87b74c8b861770f61bbd46d157bd6a15..bf9a2065c1924dc8ed91fd1bebb4e0490467f0f9 100644 GIT binary patch delta 928 zcmchVJ7^S96o&shcgDDR=;W~z6B9Qvkh`wgjT_duDKw3R-MV!MkpvOn5`?u|LBT>q z;je6rtq59-BEe1&Em8(zAwEE`ijr7Zh4tuef+wxuf&ZKPojY@fduJXLo{Zm{s7@3I z>UF9aKn}38|1&54?Pc8`fO=Rm(X#Hw_j&=vTk<%7i&0#q zU44OW8MR>D_^kz7J)^4r>u9zE6E<4H&mi3X#J@6e7PjznaD|_TC;S4&h4;f3ezA@T z(MV!m_y8UVAHj79rccqrycc$ZZn&7kEziL)1o&_mwqry z6iYa&Oa0VBNB9LM08oG?e{bnDRxerELCPKDM^0)^m%J*WQ#XLxAg diff --git a/bin/riscv64gc-unknown-none-elf.a b/bin/riscv64gc-unknown-none-elf.a index a64094439cd34e7302eb5809e0aedf51d61d76a7..8510d502d71b2f24b537ddf3108aa829b62719b5 100644 GIT binary patch delta 1049 zcmca+z0GcdWxa`!0t6&*F)%P_GcYh~(G%NHV%fwu_gTw}GD}h?A7K0lWjXT2OlD#> zU@7_!-u{eiL-U|B^B+2+ahK-pfftTKk|%*pGy^%=KJz7JG$ z6s$%aL(P@R{5;~4Pr$O87_y%x+XH2pm_WV;CJZ#dKRKUATwVq&tBWSbz@P;d*PC3* z1B)1V6m53oyTJ&Ft<4+)u~6pZ5Wz#Bz~3w;)WFKvJ$br#z2sJ)!+?l^4bAvHll6tw z8Ba_Om#}BNGkLm%z2s*cD$h+`FRC$FT+*IVVsf~oy`&D%S=dZ`05;KX@^zrfz{%oL z_L50BRDJ@hESfxB%AT=h@^z_t#?_O_iyXO=fMYs~Ku8xz2&saFXdz@PS;6YM zz~92oLhOVPm*iR#La>oQP*ceT3mb)ih1VP*?`E5D>opd6?97|l-|x*bv$K8w+w}T9 z&$)Xwh?S@i;-(PBz(uy||9lMgPz!_BPjsw#+%g<)9`i-M#MMk(FA*8N2-`N<8*|MZ*?mW=rD(0BZXj%x- zIe1JLH607lN7!KcOw(&2`W!8$4Nb>G^c9BV721M|+j37klOg92PnrJEl>cf^oZt=9 zj;7@vCPWkmaU1EO zBz=b~6`i0dl^o!k^)K^_Hq)qOl`Qpfj(QG+H5ZMG5=`u3EZ3_56zrM?@`Mu z+JT!_*{^-7(u73n2K_>trPDsr^*|bdTTnECW zU@7_!-u{eiL-U|B^B+2+ahK-pfftTKk|%*pGy^%=KJz7JG$ z6s$%aL(P@R{5;~4Pr$O87_y%x+XH2pm_WV;CJZ#dKRKUATwVq&tBWSbz@P;d*PC3* z1B)1V6m53oyTJ&Ft<4+)u~6pZ5Wz#Bz~3w;)WFKvJ$br#z2sJ)!+?l^4bAvHll6tw z8Ba_Om#}BNGkLm%z2s*cD$h+`FRC$FT+*IVVsf~oy`&D%S=dZ`05;KX@^zrfz{%oL z_L50BRDJ@hESfxB%AT=h@^z_t#?_O_iyXO=fMYs~Ku8xz2&saFXdz@PS;6YM zz~92oLhOVPm*iR#La>oQP*ceT3mb)ih1VP*?`E5D>opd6?97|l-|x*bv$K8w+w}T9 z&$)Xwh?S@i;-(PBz(uy||9lMgPz!_BPjsw#+%g<)9`i-M#MMk(FA*8N2-`N<8*|MZ*?mW=rD(0BZXj%x- zIe1JLH607lN7!KcOw(&2`W!8$4Nb>G^c9BV721M|+j37klOg92PnrJEl>cf^oZt=9 zj;7@vCPWkmaU1EO zBz=b~6`i0dl^o!k^)K^_Hq)qOl`Qpfj(QG+H5ZMG5=`u3EZ3_56zrM?@`Mu z+JT!_*{^-7(u73n2K_>trPDsr^*|bdTTnECW Date: Thu, 28 Mar 2019 19:06:40 +0300 Subject: [PATCH 7/7] Bump version (0.5.1) --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index d3e0314..2ebf0f6 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "riscv" -version = "0.5.0" +version = "0.5.1" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"]