From 5a88960ee0144cd7696c56b9a940fef45620df06 Mon Sep 17 00:00:00 2001
From: M Farkas-Dyck <strake888@gmail.com>
Date: Sat, 18 Aug 2018 10:15:10 -0800
Subject: [PATCH] use `NonZeroUsize` where appropriate

---
 src/register/misa.rs      | 18 ++++++++----------
 src/register/mvendorid.rs | 14 ++++++--------
 2 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/register/misa.rs b/src/register/misa.rs
index 119d184..8a1f061 100644
--- a/src/register/misa.rs
+++ b/src/register/misa.rs
@@ -1,9 +1,11 @@
 //! misa register
 
+use core::num::NonZeroUsize;
+
 /// misa register
 #[derive(Clone, Copy, Debug)]
 pub struct Misa {
-    bits: usize,
+    bits: NonZeroUsize,
 }
 
 /// Machine XLEN
@@ -16,16 +18,16 @@ pub enum MXL {
 impl Misa {
     /// Returns the contents of the register as raw bits
     pub fn bits(&self) -> usize {
-        self.bits
+        self.bits.get()
     }
 
     /// Returns the machine xlen.
     pub fn mxl(&self) -> MXL {
         let value = match () {
             #[cfg(target_pointer_width = "32")]
-            () => (self.bits >> 30) as u8,
+            () => (self.bits() >> 30) as u8,
             #[cfg(target_pointer_width = "64")]
-            () => (self.bits >> 62) as u8,
+            () => (self.bits() >> 62) as u8,
         };
         match value {
             1 => MXL::XLEN32,
@@ -41,7 +43,7 @@ impl Misa {
         if bit > 25 {
             return false;
         }
-        self.bits & (1 >> bit) == (1 >> bit)
+        self.bits() & (1 >> bit) == (1 >> bit)
     }
 }
 
@@ -57,11 +59,7 @@ pub fn read() -> Option<Misa> {
             }
             // When misa is hardwired to zero it means that the misa csr
             // isn't implemented.
-            if r == 0 {
-                None
-            } else {
-                Some(Misa { bits: r })
-            }
+            NonZeroUsize::new(r).map(|bits| Misa { bits })
         },
         #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
         () => unimplemented!(),
diff --git a/src/register/mvendorid.rs b/src/register/mvendorid.rs
index 553809b..37071dc 100644
--- a/src/register/mvendorid.rs
+++ b/src/register/mvendorid.rs
@@ -1,20 +1,22 @@
 //! mvendorid register
 
+use core::num::NonZeroUsize;
+
 /// mvendorid register
 #[derive(Clone, Copy, Debug)]
 pub struct Mvendorid {
-    bits: usize,
+    bits: NonZeroUsize,
 }
 
 impl Mvendorid {
     /// Returns the contents of the register as raw bits
     pub fn bits(&self) -> usize {
-        self.bits
+        self.bits.get()
     }
 
     /// Returns the JEDEC manufacturer ID
     pub fn jedec_manufacturer(&self) -> usize {
-        self.bits >> 7
+        self.bits() >> 7
     }
 }
 
@@ -30,11 +32,7 @@ pub fn read() -> Option<Mvendorid> {
             }
             // When mvendorid is hardwired to zero it means that the mvendorid
             // csr isn't implemented.
-            if r == 0 {
-                None
-            } else {
-                Some(Mvendorid { bits: r })
-            }
+            NonZeroUsize::new(r).map(|bits| Mvendorid { bits })
         }
         #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
         () => unimplemented!(),