From 45364b26a85bb7851e7def0e9ace53e660387361 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Fri, 30 Mar 2018 12:14:27 +0200
Subject: [PATCH] Add mepc register.

---
 README.md            |  2 +-
 src/register/mepc.rs | 18 ++++++++++++++++++
 src/register/mod.rs  |  1 +
 3 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 src/register/mepc.rs

diff --git a/README.md b/README.md
index 93fb329..475c535 100644
--- a/README.md
+++ b/README.md
@@ -65,7 +65,7 @@
 - [x] mtvec
 - [ ] mcounteren
 - [ ] mscratch
-- [ ] mepc
+- [x] mepc
 - [x] mcause
 - [ ] mtval
 - [x] mip
diff --git a/src/register/mepc.rs b/src/register/mepc.rs
new file mode 100644
index 0000000..c6a1307
--- /dev/null
+++ b/src/register/mepc.rs
@@ -0,0 +1,18 @@
+//! mepc register
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(target_arch = "riscv")]
+        () => {
+            let r: usize;
+            unsafe {
+                asm!("csrrs $0, 0x341, x0" : "=r"(r) ::: "volatile");
+            }
+            r as u32
+        },
+        #[cfg(not(target_arch = "riscv"))]
+        () => unimplemented!(),
+    }
+}
diff --git a/src/register/mod.rs b/src/register/mod.rs
index df94575..3387b4e 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -13,6 +13,7 @@
 pub mod mcause;
 pub mod mcycle;
 pub mod mcycleh;
+pub mod mepc;
 pub mod mie;
 pub mod mip;
 pub mod minstret;