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Merge #30 

30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>
This commit is contained in:
bors[bot] 2019-07-27 12:59:37 +00:00
parent 7f1e4a56cf b53e0a5cd2
commit 4094a32f43
2 changed files with 3 additions and 0 deletions
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3
assemble.sh
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@ -7,6 +7,9 @@ crate=riscv
# remove existing blobs because otherwise this will append object files to the old blobs # remove existing blobs because otherwise this will append object files to the old blobs
rm -f bin/*.a rm -f bin/*.a
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o
ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o

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bin/riscv32i-unknown-none-elf.a Normal file
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