Simplify #[cfg()] predicate expressions

This commit is contained in:
Vadim Kaushan 2018-12-22 09:10:20 +01:00
parent 86ac78b4aa
commit 3652547073
6 changed files with 45 additions and 32 deletions

13
build.rs Normal file
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@ -0,0 +1,13 @@
use std::env;
fn main() {
let target = env::var("TARGET").unwrap();
if target.starts_with("riscv32") {
println!("cargo:rustc-cfg=riscv");
println!("cargo:rustc-cfg=riscv32");
} else if target.starts_with("riscv64") {
println!("cargo:rustc-cfg=riscv");
println!("cargo:rustc-cfg=riscv64");
}
}

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@ -5,9 +5,9 @@ macro_rules! instruction {
#[inline] #[inline]
pub unsafe fn $fnname() { pub unsafe fn $fnname() {
match () { match () {
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
() => asm!($asm :::: "volatile"), () => asm!($asm :::: "volatile"),
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
@ -22,11 +22,11 @@ instruction!(sfence_vma_all, "sfence.vma");
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
pub unsafe fn sfence_vma(asid: usize, addr: usize) { pub unsafe fn sfence_vma(asid: usize, addr: usize) {
asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile"); asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile");
} }
#[inline] #[inline]
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
pub fn sfence_vma(_asid: usize, _addr: usize) {} pub fn sfence_vma(_asid: usize, _addr: usize) {}

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@ -8,9 +8,9 @@ use register::mstatus;
#[inline] #[inline]
pub unsafe fn disable() { pub unsafe fn disable() {
match () { match () {
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
() => mstatus::clear_mie(), () => mstatus::clear_mie(),
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
() => unimplemented!(), () => unimplemented!(),
} }
} }
@ -23,9 +23,9 @@ pub unsafe fn disable() {
#[inline] #[inline]
pub unsafe fn enable() { pub unsafe fn enable() {
match () { match () {
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
() => mstatus::set_mie(), () => mstatus::set_mie(),
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
() => unimplemented!(), () => unimplemented!(),
} }
} }

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@ -2,7 +2,7 @@ macro_rules! read_csr {
($csr_number:expr) => { ($csr_number:expr) => {
/// Reads the CSR /// Reads the CSR
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
unsafe fn _read() -> usize { unsafe fn _read() -> usize {
let r: usize; let r: usize;
asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile"); asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
@ -10,7 +10,7 @@ macro_rules! read_csr {
} }
#[inline] #[inline]
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
unsafe fn _read() -> usize { unsafe fn _read() -> usize {
unimplemented!() unimplemented!()
} }
@ -21,7 +21,7 @@ macro_rules! read_csr_rv32 {
($csr_number:expr) => { ($csr_number:expr) => {
/// Reads the CSR /// Reads the CSR
#[inline] #[inline]
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
unsafe fn _read() -> usize { unsafe fn _read() -> usize {
let r: usize; let r: usize;
asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile"); asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
@ -29,7 +29,7 @@ macro_rules! read_csr_rv32 {
} }
#[inline] #[inline]
#[cfg(not(target_arch = "riscv32"))] #[cfg(not(riscv32))]
unsafe fn _read() -> usize { unsafe fn _read() -> usize {
unimplemented!() unimplemented!()
} }
@ -76,13 +76,13 @@ macro_rules! write_csr {
($csr_number:expr) => { ($csr_number:expr) => {
/// Writes the CSR /// Writes the CSR
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
unsafe fn _write(bits: usize) { unsafe fn _write(bits: usize) {
asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"); asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
} }
#[inline] #[inline]
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
unsafe fn _write(_bits: usize) { unsafe fn _write(_bits: usize) {
unimplemented!() unimplemented!()
} }
@ -105,13 +105,13 @@ macro_rules! set {
($csr_number:expr) => { ($csr_number:expr) => {
/// Set the CSR /// Set the CSR
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
unsafe fn _set(bits: usize) { unsafe fn _set(bits: usize) {
asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"); asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
} }
#[inline] #[inline]
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
unsafe fn _set(_bits: usize) { unsafe fn _set(_bits: usize) {
unimplemented!() unimplemented!()
} }
@ -122,13 +122,13 @@ macro_rules! clear {
($csr_number:expr) => { ($csr_number:expr) => {
/// Clear the CSR /// Clear the CSR
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
unsafe fn _clear(bits: usize) { unsafe fn _clear(bits: usize) {
asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"); asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
} }
#[inline] #[inline]
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(riscv))]
unsafe fn _clear(_bits: usize) { unsafe fn _clear(_bits: usize) {
unimplemented!() unimplemented!()
} }

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@ -1,6 +1,6 @@
//! satp register //! satp register
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
use bit_field::BitField; use bit_field::BitField;
/// satp register /// satp register
@ -18,7 +18,7 @@ impl Satp {
/// Current address-translation scheme /// Current address-translation scheme
#[inline] #[inline]
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
pub fn mode(&self) -> Mode { pub fn mode(&self) -> Mode {
match self.bits.get_bit(31) { match self.bits.get_bit(31) {
false => Mode::Bare, false => Mode::Bare,
@ -28,7 +28,7 @@ impl Satp {
/// Current address-translation scheme /// Current address-translation scheme
#[inline] #[inline]
#[cfg(target_arch = "riscv64")] #[cfg(riscv64)]
pub fn mode(&self) -> Mode { pub fn mode(&self) -> Mode {
match self.bits.get_bits(60..64) { match self.bits.get_bits(60..64) {
0 => Mode::Bare, 0 => Mode::Bare,
@ -42,40 +42,40 @@ impl Satp {
/// Address space identifier /// Address space identifier
#[inline] #[inline]
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
pub fn asid(&self) -> usize { pub fn asid(&self) -> usize {
self.bits.get_bits(22..31) self.bits.get_bits(22..31)
} }
/// Address space identifier /// Address space identifier
#[inline] #[inline]
#[cfg(target_arch = "riscv64")] #[cfg(riscv64)]
pub fn asid(&self) -> usize { pub fn asid(&self) -> usize {
self.bits.get_bits(44..60) self.bits.get_bits(44..60)
} }
/// Physical page number /// Physical page number
#[inline] #[inline]
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
pub fn ppn(&self) -> usize { pub fn ppn(&self) -> usize {
self.bits.get_bits(0..22) self.bits.get_bits(0..22)
} }
/// Physical page number /// Physical page number
#[inline] #[inline]
#[cfg(target_arch = "riscv64")] #[cfg(riscv64)]
pub fn ppn(&self) -> usize { pub fn ppn(&self) -> usize {
self.bits.get_bits(0..44) self.bits.get_bits(0..44)
} }
} }
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
pub enum Mode { pub enum Mode {
Bare = 0, Bare = 0,
Sv32 = 1, Sv32 = 1,
} }
#[cfg(target_arch = "riscv64")] #[cfg(riscv64)]
pub enum Mode { pub enum Mode {
Bare = 0, Bare = 0,
Sv39 = 8, Sv39 = 8,
@ -88,7 +88,7 @@ read_csr_as!(Satp, 0x180);
write_csr!(0x180); write_csr!(0x180);
#[inline] #[inline]
#[cfg(target_arch = "riscv32")] #[cfg(riscv32)]
pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
let mut bits = 0usize; let mut bits = 0usize;
bits.set_bits(31..32, mode as usize); bits.set_bits(31..32, mode as usize);
@ -98,11 +98,11 @@ pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
} }
#[inline] #[inline]
#[cfg(target_arch = "riscv64")] #[cfg(riscv64)]
pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
let mut bits = 0usize; let mut bits = 0usize;
bits.set_bits(60..64, mode as usize); bits.set_bits(60..64, mode as usize);
bits.set_bits(44..60, asid); bits.set_bits(44..60, asid);
bits.set_bits(0..44, ppn); bits.set_bits(0..44, ppn);
_write(bits); _write(bits);
} }

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@ -123,14 +123,14 @@ set_clear_csr!(set_sum, clear_sum, 1 << 18);
/// Supervisor Previous Privilege Mode /// Supervisor Previous Privilege Mode
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
pub unsafe fn set_spp(spp: SPP) { pub unsafe fn set_spp(spp: SPP) {
_set((spp as usize) << 8); _set((spp as usize) << 8);
} }
/// The status of the floating-point unit /// The status of the floating-point unit
#[inline] #[inline]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] #[cfg(riscv)]
pub unsafe fn set_fs(fs: FS) { pub unsafe fn set_fs(fs: FS) {
_set((fs as usize) << 13); _set((fs as usize) << 13);
} }