From 31f41277022bec68d65aa09086bcb5abec4491d5 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Jun 2019 11:25:45 +0300
Subject: [PATCH] Add PMP CSRs

---
 src/register/mod.rs      |  7 ++++++-
 src/register/pmpaddrx.rs | 28 ++++++++++++++++++++++++++++
 src/register/pmpcfgx.rs  | 23 +++++++++++++++++++++++
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 src/register/pmpaddrx.rs
 create mode 100644 src/register/pmpcfgx.rs

diff --git a/src/register/mod.rs b/src/register/mod.rs
index 45487e0..82fb0a1 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -76,7 +76,12 @@ pub mod mtval;
 pub mod mip;
 
 
-// TODO: Machine Protection and Translation
+// Machine Protection and Translation
+mod pmpcfgx;
+pub use self::pmpcfgx::*;
+mod pmpaddrx;
+pub use self::pmpaddrx::*;
+
 
 // Machine Counter/Timers
 pub mod mcycle;
diff --git a/src/register/pmpaddrx.rs b/src/register/pmpaddrx.rs
new file mode 100644
index 0000000..d615dde
--- /dev/null
+++ b/src/register/pmpaddrx.rs
@@ -0,0 +1,28 @@
+macro_rules! reg {
+    (
+        $addr:expr, $csr:ident, $readf:ident, $writef:ident
+    ) => {
+        /// Physical memory protection address register
+        pub mod $csr {
+            read_csr_as_usize!($addr, $readf);
+            write_csr_as_usize!($addr, $writef);
+        }
+    }
+}
+
+reg!(0x3B0, pmpaddr0,  __read_pmpaddr0,  __write_pmpaddr0);
+reg!(0x3B1, pmpaddr1,  __read_pmpaddr1,  __write_pmpaddr1);
+reg!(0x3B2, pmpaddr2,  __read_pmpaddr2,  __write_pmpaddr2);
+reg!(0x3B3, pmpaddr3,  __read_pmpaddr3,  __write_pmpaddr3);
+reg!(0x3B4, pmpaddr4,  __read_pmpaddr4,  __write_pmpaddr4);
+reg!(0x3B5, pmpaddr5,  __read_pmpaddr5,  __write_pmpaddr5);
+reg!(0x3B6, pmpaddr6,  __read_pmpaddr6,  __write_pmpaddr6);
+reg!(0x3B7, pmpaddr7,  __read_pmpaddr7,  __write_pmpaddr7);
+reg!(0x3B8, pmpaddr8,  __read_pmpaddr8,  __write_pmpaddr8);
+reg!(0x3B9, pmpaddr9,  __read_pmpaddr9,  __write_pmpaddr9);
+reg!(0x3BA, pmpaddr10, __read_pmpaddr10, __write_pmpaddr10);
+reg!(0x3BB, pmpaddr11, __read_pmpaddr11, __write_pmpaddr11);
+reg!(0x3BC, pmpaddr12, __read_pmpaddr12, __write_pmpaddr12);
+reg!(0x3BD, pmpaddr13, __read_pmpaddr13, __write_pmpaddr13);
+reg!(0x3BE, pmpaddr14, __read_pmpaddr14, __write_pmpaddr14);
+reg!(0x3BF, pmpaddr15, __read_pmpaddr15, __write_pmpaddr15);
diff --git a/src/register/pmpcfgx.rs b/src/register/pmpcfgx.rs
new file mode 100644
index 0000000..ec27251
--- /dev/null
+++ b/src/register/pmpcfgx.rs
@@ -0,0 +1,23 @@
+/// Physical memory protection configuration
+pub mod pmpcfg0 {
+    read_csr_as_usize!(0x3A0, __read_pmpcfg0);
+    write_csr_as_usize!(0x3A0, __write_pmpcfg0);
+}
+
+/// Physical memory protection configuration, RV32 only
+pub mod pmpcfg1 {
+    read_csr_as_usize_rv32!(0x3A1, __read_pmpcfg1);
+    write_csr_as_usize_rv32!(0x3A1, __write_pmpcfg1);
+}
+
+/// Physical memory protection configuration
+pub mod pmpcfg2 {
+    read_csr_as_usize!(0x3A2, __read_pmpcfg2);
+    write_csr_as_usize!(0x3A2, __write_pmpcfg2);
+}
+
+/// Physical memory protection configuration, RV32 only
+pub mod pmpcfg3 {
+    read_csr_as_usize_rv32!(0x3A3, __read_pmpcfg3);
+    write_csr_as_usize_rv32!(0x3A3, __write_pmpcfg3);
+}