From 427c3b90352565dbacdcbec7159b67ad027e8657 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 1 Mar 2019 17:00:36 +0300 Subject: [PATCH 1/5] Generate binaries for 64-bit targets --- assemble.sh | 6 +++++- bin/riscv64gc-unknown-none-elf.a | Bin 0 -> 6980 bytes bin/riscv64imac-unknown-none-elf.a | Bin 0 -> 6980 bytes 3 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 bin/riscv64gc-unknown-none-elf.a create mode 100644 bin/riscv64imac-unknown-none-elf.a diff --git a/assemble.sh b/assemble.sh index 30e6fd2..e89b5d5 100755 --- a/assemble.sh +++ b/assemble.sh @@ -10,7 +10,11 @@ rm -f bin/*.a riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm32.S -o bin/$crate-32.o ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o bin/$crate-32.o -cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a +ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o bin/$crate-32.o + +riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o +ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o +ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o rm bin/$crate.o rm bin/$crate-32.o diff --git a/bin/riscv64gc-unknown-none-elf.a b/bin/riscv64gc-unknown-none-elf.a new file mode 100644 index 0000000000000000000000000000000000000000..124ca149bdf859de31a68937e7f98d1d6dc7d8bc GIT binary patch literal 6980 zcmeI0O^6&t6vu0~Ge*~swE6Zc_D0)}xQwGNu%xIu5A<=}53Ts>&#<%QQ-lNIO>6GUH`!J!U#g;0o3Ty)^0eO-pwTla84sc~UK-6e0@^oQ2i!54walPdTRW%2 z2!0&f$Sqmsmz?(ci5T=`JZv7$wlBAD+tbsyU)v8pU^ec7i5F*PpBNt-Q`=YDnD|YM zT9yj&)b+Mshz?deVoKa6#$P+WF2$S=rPvJRDJa8W8cJ~zN+0W;mZ}FcP`0oP1MKZ! zuMa#F=+i(SEW~A`s<85IF#IZpZ)Et@48Mlq@HnI9 ziEAlT#1q#s+-#asuP1IO5#98}CWiYAzmega8NP+#TN%EM;oBL$gW)?FeiOrQX80`( zzm?&)F?<)pZ)bSG@JWX6X80WpzmwtWFSWuvaaRR}eRwy+?;#wXaehVI!Or(9;tqD8 zFKFDs9qyC!lPcYBf3xO*Bojk|rwY1~D~Y1|z`PUCJ3IgPtlk<++)9XXA=caYP# z`xrTmyU&r+xI2fO#@)BbY1~~zPUG$m|GS=$Seak0UR$olBEY)&Mw#rDQTo#$R3%4AVn0}FG@s$Ahhf$AAa>D2^ zgOxLkNuw`k7@QvF${Rev;k0t4`YEOTr|U0gIOX{tVf2qH4pu&SmGw_5pQ`!cTm@FA z->-bC^mC}L*FVST;rs?xH~-7Zr)vIZQC+Wpo6#>g>OW%iOOE=}jDE#Y{}rQ89rZsl z`sW?>zcc!EM}0&6cvZjOD~|ddjQ)h9eu~k*%)O+d= zO$|Y=^BYI~7DoTQqdsKx7aa9%Mt{*!Kg;MZIqG9Zf7wxgl+pj`s6WBz|8ms7$LKe} zrchS5|4%Xc2}k`|Mi1``T;~6Q(QkLugPR(HSYY&X8+F$n^>wfMz*!B;DFr#zArb literal 0 HcmV?d00001 diff --git a/bin/riscv64imac-unknown-none-elf.a b/bin/riscv64imac-unknown-none-elf.a new file mode 100644 index 0000000000000000000000000000000000000000..124ca149bdf859de31a68937e7f98d1d6dc7d8bc GIT binary patch literal 6980 zcmeI0O^6&t6vu0~Ge*~swE6Zc_D0)}xQwGNu%xIu5A<=}53Ts>&#<%QQ-lNIO>6GUH`!J!U#g;0o3Ty)^0eO-pwTla84sc~UK-6e0@^oQ2i!54walPdTRW%2 z2!0&f$Sqmsmz?(ci5T=`JZv7$wlBAD+tbsyU)v8pU^ec7i5F*PpBNt-Q`=YDnD|YM zT9yj&)b+Mshz?deVoKa6#$P+WF2$S=rPvJRDJa8W8cJ~zN+0W;mZ}FcP`0oP1MKZ! zuMa#F=+i(SEW~A`s<85IF#IZpZ)Et@48Mlq@HnI9 ziEAlT#1q#s+-#asuP1IO5#98}CWiYAzmega8NP+#TN%EM;oBL$gW)?FeiOrQX80`( zzm?&)F?<)pZ)bSG@JWX6X80WpzmwtWFSWuvaaRR}eRwy+?;#wXaehVI!Or(9;tqD8 zFKFDs9qyC!lPcYBf3xO*Bojk|rwY1~D~Y1|z`PUCJ3IgPtlk<++)9XXA=caYP# z`xrTmyU&r+xI2fO#@)BbY1~~zPUG$m|GS=$Seak0UR$olBEY)&Mw#rDQTo#$R3%4AVn0}FG@s$Ahhf$AAa>D2^ zgOxLkNuw`k7@QvF${Rev;k0t4`YEOTr|U0gIOX{tVf2qH4pu&SmGw_5pQ`!cTm@FA z->-bC^mC}L*FVST;rs?xH~-7Zr)vIZQC+Wpo6#>g>OW%iOOE=}jDE#Y{}rQ89rZsl z`sW?>zcc!EM}0&6cvZjOD~|ddjQ)h9eu~k*%)O+d= zO$|Y=^BYI~7DoTQqdsKx7aa9%Mt{*!Kg;MZIqG9Zf7wxgl+pj`s6WBz|8ms7$LKe} zrchS5|4%Xc2}k`|Mi1``T;~6Q(QkLugPR(HSYY&X8+F$n^>wfMz*!B;DFr#zArb literal 0 HcmV?d00001 From ab15a6a8c786b6cb4a3a1be344021d2de32f03ea Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 1 Mar 2019 17:02:13 +0300 Subject: [PATCH 2/5] CI: check new targets --- .travis.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.travis.yml b/.travis.yml index 01ba0e8..78d1336 100644 --- a/.travis.yml +++ b/.travis.yml @@ -24,6 +24,14 @@ matrix: rust: nightly if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + - env: TARGET=riscv64imac-unknown-none-elf + rust: nightly + if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + + - env: TARGET=riscv64gc-unknown-none-elf + rust: nightly + if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + - env: TARGET=x86_64-unknown-linux-gnu rust: stable if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) From b665adeb95b131e04d2d6f2e0a45b55398420498 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 1 Mar 2019 17:10:45 +0300 Subject: [PATCH 3/5] Refactoring: use get_bit() instead of shifts --- src/register/mie.rs | 20 +++++++++++--------- src/register/mip.rs | 20 +++++++++++--------- 2 files changed, 22 insertions(+), 18 deletions(-) diff --git a/src/register/mie.rs b/src/register/mie.rs index c55a52d..121a5b5 100644 --- a/src/register/mie.rs +++ b/src/register/mie.rs @@ -1,5 +1,7 @@ //! mie register +use bit_field::BitField; + /// mie register #[derive(Clone, Copy, Debug)] pub struct Mie { @@ -16,55 +18,55 @@ impl Mie { /// User Software Interrupt Enable #[inline] pub fn usoft(&self) -> bool { - self.bits & (1 << 0) == 1 << 0 + self.bits.get_bit(0) } /// Supervisor Software Interrupt Enable #[inline] pub fn ssoft(&self) -> bool { - self.bits & (1 << 1) == 1 << 1 + self.bits.get_bit(1) } /// Machine Software Interrupt Enable #[inline] pub fn msoft(&self) -> bool { - self.bits & (1 << 3) == 1 << 3 + self.bits.get_bit(3) } /// User Timer Interrupt Enable #[inline] pub fn utimer(&self) -> bool { - self.bits & (1 << 4) == 1 << 4 + self.bits.get_bit(4) } /// Supervisor Timer Interrupt Enable #[inline] pub fn stimer(&self) -> bool { - self.bits & (1 << 5) == 1 << 5 + self.bits.get_bit(5) } /// Machine Timer Interrupt Enable #[inline] pub fn mtimer(&self) -> bool { - self.bits & (1 << 7) == 1 << 7 + self.bits.get_bit(7) } /// User External Interrupt Enable #[inline] pub fn uext(&self) -> bool { - self.bits & (1 << 8) == 1 << 8 + self.bits.get_bit(8) } /// Supervisor External Interrupt Enable #[inline] pub fn sext(&self) -> bool { - self.bits & (1 << 9) == 1 << 9 + self.bits.get_bit(9) } /// Machine External Interrupt Enable #[inline] pub fn mext(&self) -> bool { - self.bits & (1 << 11) == 1 << 11 + self.bits.get_bit(11) } } diff --git a/src/register/mip.rs b/src/register/mip.rs index 076a019..6633088 100644 --- a/src/register/mip.rs +++ b/src/register/mip.rs @@ -1,5 +1,7 @@ //! mip register +use bit_field::BitField; + /// mip register #[derive(Clone, Copy, Debug)] pub struct Mip { @@ -16,55 +18,55 @@ impl Mip { /// User Software Interrupt Pending #[inline] pub fn usoft(&self) -> bool { - self.bits & (1 << 0) == 1 << 0 + self.bits.get_bit(0) } /// Supervisor Software Interrupt Pending #[inline] pub fn ssoft(&self) -> bool { - self.bits & (1 << 1) == 1 << 1 + self.bits.get_bit(1) } /// Machine Software Interrupt Pending #[inline] pub fn msoft(&self) -> bool { - self.bits & (1 << 3) == 1 << 3 + self.bits.get_bit(3) } /// User Timer Interrupt Pending #[inline] pub fn utimer(&self) -> bool { - self.bits & (1 << 4) == 1 << 4 + self.bits.get_bit(4) } /// Supervisor Timer Interrupt Pending #[inline] pub fn stimer(&self) -> bool { - self.bits & (1 << 5) == 1 << 5 + self.bits.get_bit(5) } /// Machine Timer Interrupt Pending #[inline] pub fn mtimer(&self) -> bool { - self.bits & (1 << 7) == 1 << 7 + self.bits.get_bit(7) } /// User External Interrupt Pending #[inline] pub fn uext(&self) -> bool { - self.bits & (1 << 8) == 1 << 8 + self.bits.get_bit(8) } /// Supervisor External Interrupt Pending #[inline] pub fn sext(&self) -> bool { - self.bits & (1 << 9) == 1 << 9 + self.bits.get_bit(9) } /// Machine External Interrupt Pending #[inline] pub fn mext(&self) -> bool { - self.bits & (1 << 11) == 1 << 11 + self.bits.get_bit(11) } } From 925c4969499138f569bb0fd1b1daae9fbda0fda7 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 1 Mar 2019 17:41:41 +0300 Subject: [PATCH 4/5] Read composite CSRs as one 64-bit value --- src/register/macros.rs | 22 ++++++++++++++++++++++ src/register/mcycle.rs | 1 + src/register/minstret.rs | 1 + src/register/time.rs | 1 + 4 files changed, 25 insertions(+) diff --git a/src/register/macros.rs b/src/register/macros.rs index d46d3a4..02fc424 100644 --- a/src/register/macros.rs +++ b/src/register/macros.rs @@ -208,3 +208,25 @@ macro_rules! set_clear_csr { clear_csr!($(#[$attr])*, $clear_field, $e); } } + +macro_rules! read_composite_csr { + ($hi:expr, $lo:expr) => { + /// Reads the CSR as a 64-bit value + #[inline] + pub fn read64() -> u64 { + match () { + #[cfg(riscv32)] + () => loop { + let hi = $hi; + let lo = $lo; + if hi == $hi { + return ((hi as u64) << 32) | lo as u64; + } + }, + + #[cfg(not(riscv32))] + () => $lo as u64, + } + } + } +} diff --git a/src/register/mcycle.rs b/src/register/mcycle.rs index 41e8115..95d172b 100644 --- a/src/register/mcycle.rs +++ b/src/register/mcycle.rs @@ -1,3 +1,4 @@ //! mcycle register read_csr_as_usize!(0xB00, __read_mcycle); +read_composite_csr!(super::mcycleh::read(), read()); diff --git a/src/register/minstret.rs b/src/register/minstret.rs index 6aba6b3..d553dd8 100644 --- a/src/register/minstret.rs +++ b/src/register/minstret.rs @@ -1,3 +1,4 @@ //! minstret register read_csr_as_usize!(0xB02, __read_minstret); +read_composite_csr!(super::minstreth::read(), read()); diff --git a/src/register/time.rs b/src/register/time.rs index 8793475..665b507 100644 --- a/src/register/time.rs +++ b/src/register/time.rs @@ -1,3 +1,4 @@ //! time register read_csr_as_usize!(0xC01, __read_time); +read_composite_csr!(super::timeh::read(), read()); From a091d236ddaf167c3159bda5000a5dfcfdf9ae5e Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 1 Mar 2019 17:48:59 +0300 Subject: [PATCH 5/5] Bump version --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 3b19516..d3e0314 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "riscv" -version = "0.4.0" +version = "0.5.0" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"]