Remove inline(always).
This commit is contained in:
David Craven
parent
21bfaf49ae
commit
179df42984
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@ -2,7 +2,7 @@
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macro_rules! instruction {
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($fnname:ident, $asm:expr) => (
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#[inline(always)]
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#[inline]
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pub fn $fnname() {
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match () {
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#[cfg(target_arch = "riscv")]
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102
src/csr.rs
102
src/csr.rs
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@ -32,14 +32,14 @@ macro_rules! r {
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}
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impl super::$TYPE {
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#[inline(always)]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: csr_asm!(csrrs, $CSR, 0) as u32 }
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}
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}
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impl R {
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#[inline(always)]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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@ -74,17 +74,17 @@ macro_rules! w {
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}
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impl W {
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#[inline(always)]
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#[inline]
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pub fn bits(&mut self, value: u32) -> &mut W {
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self.bits = value;
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self
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}
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#[inline(always)]
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#[inline]
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pub fn set_bits(&mut self, value: u32) -> &mut W {
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self.bits |= value;
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self
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}
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#[inline(always)]
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#[inline]
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pub fn clear_bits(&mut self, value: u32) -> &mut W {
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self.bits &= !value;
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self
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@ -280,7 +280,7 @@ impl Exception {
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impl mcause::R {
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#[inline(always)]
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#[inline]
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/// Trap Cause
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pub fn cause(&self) -> Trap {
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let bits = self.bits();
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@ -291,7 +291,7 @@ impl mcause::R {
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}
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}
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#[inline(always)]
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#[inline]
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/// Is trap cause an interrupt.
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pub fn is_interrupt(&self) -> bool {
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match self.cause() {
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@ -300,7 +300,7 @@ impl mcause::R {
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}
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}
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#[inline(always)]
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#[inline]
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/// Is trap cause an exception.
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pub fn is_exception(&self) -> bool {
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match self.cause() {
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@ -328,43 +328,43 @@ pub enum SPP {
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impl mstatus::R {
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#[inline(always)]
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#[inline]
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/// User Interrupt Enable
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pub fn uie(&self) -> bool {
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self.bits() & (1 << 0) == 1 << 0
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Interrupt Enable
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pub fn sie(&self) -> bool {
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self.bits() & (1 << 1) == 1 << 1
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}
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#[inline(always)]
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#[inline]
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/// Machine Interrupt Enable
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pub fn mie(&self) -> bool {
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self.bits() & (1 << 3) == 1 << 3
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}
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#[inline(always)]
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#[inline]
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/// User Previous Interrupt Enable
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pub fn upie(&self) -> bool {
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self.bits() & (1 << 4) == 1 << 4
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Previous Interrupt Enable
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pub fn spie(&self) -> bool {
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self.bits() & (1 << 5) == 1 << 5
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}
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#[inline(always)]
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#[inline]
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/// User Previous Interrupt Enable
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pub fn mpie(&self) -> bool {
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self.bits() & (1 << 7) == 1 << 7
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Previous Privilege Mode
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pub fn spp(&self) -> SPP {
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match self.bits() & (1 << 8) == (1 << 8) {
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@ -373,7 +373,7 @@ impl mstatus::R {
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}
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}
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#[inline(always)]
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#[inline]
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/// Machine Previous Privilege Mode
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pub fn mpp(&self) -> MPP {
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match (self.bits() & (0b11 << 11)) >> 11 {
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@ -386,49 +386,49 @@ impl mstatus::R {
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}
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impl mstatus::W {
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#[inline(always)]
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#[inline]
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/// User Interrupt Enable
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pub fn uie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 0)
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Interrupt Enable
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pub fn sie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 1)
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}
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#[inline(always)]
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#[inline]
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/// Machine Interrupt Enable
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pub fn mie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 3)
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}
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#[inline(always)]
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#[inline]
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/// User Previous Interrupt Enable
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pub fn upie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 4)
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}
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#[inline(always)]
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#[inline]
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/// User Previous Interrupt Enable
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pub fn spie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 5)
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}
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#[inline(always)]
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#[inline]
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/// User Previous Interrupt Enable
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pub fn mpie(&mut self) -> &mut mstatus::W {
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self.set_bits(1 << 7)
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Previous Privilege Mode
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pub fn spp(&mut self, value: SPP) -> &mut mstatus::W {
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self.set_bits((value as u32) << 8)
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}
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#[inline(always)]
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#[inline]
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/// Machine Previous Privilege Mode
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pub fn mpp(&mut self, value: MPP) -> &mut mstatus::W {
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self.set_bits((value as u32) << 11)
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@ -437,55 +437,55 @@ impl mstatus::W {
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/// Machine Interrupt Enable CSR (mie) is ReadWrite.
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impl mie::R {
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#[inline(always)]
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#[inline]
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/// User Software Interrupt Enable
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pub fn usoft(&self) -> bool {
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self.bits() & (1 << 0) == 1 << 0
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Software Interrupt Enable
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pub fn ssoft(&self) -> bool {
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self.bits() & (1 << 1) == 1 << 1
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}
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#[inline(always)]
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#[inline]
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/// Machine Software Interrupt Enable
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pub fn msoft(&self) -> bool {
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self.bits() & (1 << 3) == 1 << 3
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}
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#[inline(always)]
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#[inline]
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/// User Timer Interrupt Enable
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pub fn utimer(&self) -> bool {
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self.bits() & (1 << 4) == 1 << 4
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Timer Interrupt Enable
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pub fn stimer(&self) -> bool {
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self.bits() & (1 << 5) == 1 << 5
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}
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#[inline(always)]
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#[inline]
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/// Machine Timer Interrupt Enable
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pub fn mtimer(&self) -> bool {
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self.bits() & (1 << 7) == 1 << 7
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}
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#[inline(always)]
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#[inline]
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/// User External Interrupt Enable
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pub fn uext(&self) -> bool {
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self.bits() & (1 << 8) == 1 << 8
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}
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#[inline(always)]
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#[inline]
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/// Supervisor External Interrupt Enable
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pub fn sext(&self) -> bool {
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self.bits() & (1 << 9) == 1 << 9
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}
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#[inline(always)]
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#[inline]
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/// Machine External Interrupt Enable
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pub fn mext(&self) -> bool {
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self.bits() & (1 << 11) == 1 << 11
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@ -493,55 +493,55 @@ impl mie::R {
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}
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impl mie::W {
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#[inline(always)]
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#[inline]
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/// User Software Interrupt Enable
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pub fn usoft(&mut self) -> &mut mie::W {
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self.set_bits(1 << 0)
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Software Interrupt Enable
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pub fn ssoft(&mut self) -> &mut mie::W {
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self.set_bits(1 << 1)
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}
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#[inline(always)]
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#[inline]
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/// Machine Software Interrupt Enable
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pub fn msoft(&mut self) -> &mut mie::W {
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self.set_bits(1 << 3)
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}
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#[inline(always)]
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#[inline]
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/// User Timer Interrupt Enable
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pub fn utimer(&mut self) -> &mut mie::W {
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self.set_bits(1 << 4)
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Timer Interrupt Enable
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pub fn stimer(&mut self) -> &mut mie::W {
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self.set_bits(1 << 5)
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}
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#[inline(always)]
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#[inline]
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/// Machine Timer Interrupt Enable
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pub fn mtimer(&mut self) -> &mut mie::W {
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self.set_bits(1 << 7)
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}
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#[inline(always)]
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#[inline]
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/// User External Interrupt Enable
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pub fn uext(&mut self) -> &mut mie::W {
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self.set_bits(1 << 8)
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}
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#[inline(always)]
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#[inline]
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/// Supervisor External Interrupt Enable
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pub fn sext(&mut self) -> &mut mie::W {
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self.set_bits(1 << 9)
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}
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#[inline(always)]
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#[inline]
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/// Machine External Interrupt Enable
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pub fn mext(&mut self) -> &mut mie::W {
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self.set_bits(1 << 11)
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@ -550,55 +550,55 @@ impl mie::W {
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/// Machine Interrupt Pending CSR (mip) is ReadOnly.
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impl mip::R {
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#[inline(always)]
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#[inline]
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/// User Software Interrupt Enable
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pub fn usoft(&self) -> bool {
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self.bits() & (1 << 0) == 1 << 0
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Software Interrupt Enable
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pub fn ssoft(&self) -> bool {
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self.bits() & (1 << 1) == 1 << 1
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}
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#[inline(always)]
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#[inline]
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/// Machine Software Interrupt Enable
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pub fn msoft(&self) -> bool {
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self.bits() & (1 << 3) == 1 << 3
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}
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#[inline(always)]
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#[inline]
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/// User Timer Interrupt Enable
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pub fn utimer(&self) -> bool {
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self.bits() & (1 << 4) == 1 << 4
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}
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#[inline(always)]
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#[inline]
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/// Supervisor Timer Interrupt Enable
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pub fn stimer(&self) -> bool {
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self.bits() & (1 << 5) == 1 << 5
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}
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#[inline(always)]
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#[inline]
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/// Machine Timer Interrupt Enable
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pub fn mtimer(&self) -> bool {
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self.bits() & (1 << 7) == 1 << 7
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}
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#[inline(always)]
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#[inline]
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/// User External Interrupt Enable
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pub fn uext(&self) -> bool {
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self.bits() & (1 << 8) == 1 << 8
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}
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#[inline(always)]
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#[inline]
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/// Supervisor External Interrupt Enable
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pub fn sext(&self) -> bool {
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self.bits() & (1 << 9) == 1 << 9
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}
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#[inline(always)]
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#[inline]
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/// Machine External Interrupt Enable
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pub fn mext(&self) -> bool {
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self.bits() & (1 << 11) == 1 << 11
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@ -4,7 +4,7 @@
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pub use bare_metal::{CriticalSection, Mutex, Nr};
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/// Disables all interrupts
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#[inline(always)]
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#[inline]
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pub fn disable() {
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match () {
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#[cfg(target_arch = "riscv")]
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@ -19,7 +19,7 @@ pub fn disable() {
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/// # Safety
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///
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/// - Do not call this function inside an `interrupt::free` critical section
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#[inline(always)]
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#[inline]
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pub unsafe fn enable() {
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match () {
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#[cfg(target_arch = "riscv")]
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