diff --git a/src/asm.rs b/src/asm.rs
index d258383..cf451a3 100644
--- a/src/asm.rs
+++ b/src/asm.rs
@@ -1,7 +1,7 @@
 //! Assembly instructions
 
 macro_rules! instruction {
-    ($fnname:ident, $asm:expr) => (
+    ($fnname:ident, $asm:expr, $asm_fn:ident) => (
         #[inline]
         pub unsafe fn $fnname() {
             match () {
@@ -9,7 +9,13 @@ macro_rules! instruction {
                 () => asm!($asm :::: "volatile"),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn();
+                    }
+
+                    $asm_fn();
+                }
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -20,9 +26,9 @@ macro_rules! instruction {
 
 
 /// Priviledged ISA Instructions
-instruction!(ebreak, "ebreak");
-instruction!(wfi, "wfi");
-instruction!(sfence_vma_all, "sfence.vma");
+instruction!(ebreak, "ebreak", __ebreak);
+instruction!(wfi, "wfi", __wfi);
+instruction!(sfence_vma_all, "sfence.vma", __sfence_vma_all);
 
 
 #[inline]
@@ -33,7 +39,13 @@ pub unsafe fn sfence_vma(asid: usize, addr: usize) {
         () => asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile"),
 
         #[cfg(all(riscv, not(feature = "inline-asm")))]
-        () => unimplemented!(),
+        () => {
+            extern "C" {
+                fn __sfence_vma(asid: usize, addr: usize);
+            }
+
+            __sfence_vma(asid, addr);
+        }
 
         #[cfg(not(riscv))]
         () => unimplemented!(),
diff --git a/src/register/macros.rs b/src/register/macros.rs
index 7520584..cda38ac 100644
--- a/src/register/macros.rs
+++ b/src/register/macros.rs
@@ -1,5 +1,5 @@
 macro_rules! read_csr {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Reads the CSR
         #[inline]
         unsafe fn _read() -> usize {
@@ -12,7 +12,13 @@ macro_rules! read_csr {
                 }
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn() -> usize;
+                    }
+
+                    $asm_fn()
+                }
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -22,7 +28,7 @@ macro_rules! read_csr {
 }
 
 macro_rules! read_csr_rv32 {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Reads the CSR
         #[inline]
         unsafe fn _read() -> usize {
@@ -35,7 +41,13 @@ macro_rules! read_csr_rv32 {
                 }
 
                 #[cfg(all(riscv32, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn() -> usize;
+                    }
+
+                    $asm_fn()
+                }
 
                 #[cfg(not(riscv32))]
                 () => unimplemented!(),
@@ -45,8 +57,8 @@ macro_rules! read_csr_rv32 {
 }
 
 macro_rules! read_csr_as {
-    ($register:ident, $csr_number:expr) => {
-        read_csr!($csr_number);
+    ($register:ident, $csr_number:expr, $asm_fn: ident) => {
+        read_csr!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -57,8 +69,8 @@ macro_rules! read_csr_as {
 }
 
 macro_rules! read_csr_as_usize {
-    ($csr_number:expr) => {
-        read_csr!($csr_number);
+    ($csr_number:expr, $asm_fn: ident) => {
+        read_csr!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -69,8 +81,8 @@ macro_rules! read_csr_as_usize {
 }
 
 macro_rules! read_csr_as_usize_rv32 {
-    ($csr_number:expr) => {
-        read_csr_rv32!($csr_number);
+    ($csr_number:expr, $asm_fn: ident) => {
+        read_csr_rv32!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -81,7 +93,7 @@ macro_rules! read_csr_as_usize_rv32 {
 }
 
 macro_rules! write_csr {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Writes the CSR
         #[inline]
         #[allow(unused_variables)]
@@ -91,7 +103,13 @@ macro_rules! write_csr {
                 () => asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
+                    }
+
+                    $asm_fn(bits);
+                }
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -101,8 +119,8 @@ macro_rules! write_csr {
 }
 
 macro_rules! write_csr_as_usize {
-    ($csr_number:expr) => {
-        write_csr!($csr_number);
+    ($csr_number:expr, $asm_fn: ident) => {
+        write_csr!($csr_number, $asm_fn);
 
         /// Writes the CSR
         #[inline]
@@ -113,7 +131,7 @@ macro_rules! write_csr_as_usize {
 }
 
 macro_rules! set {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Set the CSR
         #[inline]
         #[allow(unused_variables)]
@@ -123,7 +141,13 @@ macro_rules! set {
                 () => asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
+                    }
+
+                    $asm_fn(bits);
+                }
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -133,7 +157,7 @@ macro_rules! set {
 }
 
 macro_rules! clear {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Clear the CSR
         #[inline]
         #[allow(unused_variables)]
@@ -143,7 +167,13 @@ macro_rules! clear {
                 () => asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => unimplemented!(),
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
+                    }
+
+                    $asm_fn(bits);
+                }
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
diff --git a/src/register/mcause.rs b/src/register/mcause.rs
index e659383..67e6d8c 100644
--- a/src/register/mcause.rs
+++ b/src/register/mcause.rs
@@ -136,4 +136,4 @@ impl Mcause {
     }
 }
 
-read_csr_as!(Mcause, 0x342);
+read_csr_as!(Mcause, 0x342, __read_mcause);
diff --git a/src/register/mcycle.rs b/src/register/mcycle.rs
index f2905fc..41e8115 100644
--- a/src/register/mcycle.rs
+++ b/src/register/mcycle.rs
@@ -1,3 +1,3 @@
 //! mcycle register
 
-read_csr_as_usize!(0xB00);
+read_csr_as_usize!(0xB00, __read_mcycle);
diff --git a/src/register/mcycleh.rs b/src/register/mcycleh.rs
index 31ca70c..784dca4 100644
--- a/src/register/mcycleh.rs
+++ b/src/register/mcycleh.rs
@@ -1,3 +1,3 @@
 //! mcycleh register
 
-read_csr_as_usize_rv32!(0xB80);
+read_csr_as_usize_rv32!(0xB80, __read_mcycleh);
diff --git a/src/register/mepc.rs b/src/register/mepc.rs
index 4fc7863..9871513 100644
--- a/src/register/mepc.rs
+++ b/src/register/mepc.rs
@@ -1,3 +1,3 @@
 //! mepc register
 
-read_csr_as_usize!(0x341);
+read_csr_as_usize!(0x341, __read_mepc);
diff --git a/src/register/mie.rs b/src/register/mie.rs
index 0828cd8..cd4fcc2 100644
--- a/src/register/mie.rs
+++ b/src/register/mie.rs
@@ -68,9 +68,9 @@ impl Mie {
     }
 }
 
-read_csr_as!(Mie, 0x304);
-set!(0x304);
-clear!(0x304);
+read_csr_as!(Mie, 0x304, __read_mie);
+set!(0x304, __set_mie);
+clear!(0x304, __clear_mie);
 
 /// User Software Interrupt Enable
 set_clear_csr!(set_usoft, clear_usoft, 1 << 0);
diff --git a/src/register/minstret.rs b/src/register/minstret.rs
index aa072fd..6aba6b3 100644
--- a/src/register/minstret.rs
+++ b/src/register/minstret.rs
@@ -1,3 +1,3 @@
 //! minstret register
 
-read_csr_as_usize!(0xB02);
+read_csr_as_usize!(0xB02, __read_minstret);
diff --git a/src/register/minstreth.rs b/src/register/minstreth.rs
index 5548399..56bc54e 100644
--- a/src/register/minstreth.rs
+++ b/src/register/minstreth.rs
@@ -1,3 +1,3 @@
 //! minstreth register
 
-read_csr_as_usize_rv32!(0xB82);
+read_csr_as_usize_rv32!(0xB82, __read_minstreth);
diff --git a/src/register/mip.rs b/src/register/mip.rs
index 39f1edd..076a019 100644
--- a/src/register/mip.rs
+++ b/src/register/mip.rs
@@ -68,4 +68,4 @@ impl Mip {
     }
 }
 
-read_csr_as!(Mip, 0x344);
+read_csr_as!(Mip, 0x344, __read_mip);
diff --git a/src/register/misa.rs b/src/register/misa.rs
index 9a2482d..bd52508 100644
--- a/src/register/misa.rs
+++ b/src/register/misa.rs
@@ -47,7 +47,7 @@ impl Misa {
     }
 }
 
-read_csr!(0x301);
+read_csr!(0x301, __read_misa);
 
 /// Reads the CSR
 #[inline]
diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs
index 30ba4ec..f49967a 100644
--- a/src/register/mstatus.rs
+++ b/src/register/mstatus.rs
@@ -79,9 +79,9 @@ impl Mstatus {
 }
 
 
-read_csr_as!(Mstatus, 0x300);
-set!(0x300);
-clear!(0x300);
+read_csr_as!(Mstatus, 0x300, __read_mstatus);
+set!(0x300, __set_mstatus);
+clear!(0x300, __clear_mstatus);
 
 /// User Interrupt Enable
 set_clear_csr!(set_uie, clear_uie, 1 << 0);
diff --git a/src/register/mtvec.rs b/src/register/mtvec.rs
index efa475e..d4f8c07 100644
--- a/src/register/mtvec.rs
+++ b/src/register/mtvec.rs
@@ -34,9 +34,9 @@ impl Mtvec {
     }
 }
 
-read_csr_as!(Mtvec, 0x305);
+read_csr_as!(Mtvec, 0x305, __read_mtvec);
 
-write_csr!(0x305);
+write_csr!(0x305, __write_mtvec);
 
 /// Writes the CSR
 #[inline]
diff --git a/src/register/mvendorid.rs b/src/register/mvendorid.rs
index c2f831f..a76ffb8 100644
--- a/src/register/mvendorid.rs
+++ b/src/register/mvendorid.rs
@@ -20,7 +20,7 @@ impl Mvendorid {
     }
 }
 
-read_csr!(0xF11);
+read_csr!(0xF11, __read_mvendorid);
 
 /// Reads the CSR
 #[inline]
diff --git a/src/register/satp.rs b/src/register/satp.rs
index 2f00334..fa0c6ee 100644
--- a/src/register/satp.rs
+++ b/src/register/satp.rs
@@ -84,8 +84,8 @@ pub enum Mode {
     Sv64 = 11,
 }
 
-read_csr_as!(Satp, 0x180);
-write_csr!(0x180);
+read_csr_as!(Satp, 0x180, __read_satp);
+write_csr!(0x180, __write_satp);
 
 #[inline]
 #[cfg(riscv32)]
diff --git a/src/register/scause.rs b/src/register/scause.rs
index 505202d..596ccef 100644
--- a/src/register/scause.rs
+++ b/src/register/scause.rs
@@ -115,4 +115,4 @@ impl Scause {
     }
 }
 
-read_csr_as!(Scause, 0x142);
+read_csr_as!(Scause, 0x142, __read_scause);
diff --git a/src/register/sepc.rs b/src/register/sepc.rs
index a39d1bd..aba69df 100644
--- a/src/register/sepc.rs
+++ b/src/register/sepc.rs
@@ -1,4 +1,4 @@
 //! sepc register
 
-read_csr_as_usize!(0x141);
-write_csr_as_usize!(0x141);
+read_csr_as_usize!(0x141, __read_sepc);
+write_csr_as_usize!(0x141, __write_sepc);
diff --git a/src/register/sie.rs b/src/register/sie.rs
index 10d3845..1ea8a7c 100644
--- a/src/register/sie.rs
+++ b/src/register/sie.rs
@@ -52,9 +52,9 @@ impl Sie {
     }
 }
 
-read_csr_as!(Sie, 0x104);
-set!(0x104);
-clear!(0x104);
+read_csr_as!(Sie, 0x104, __read_sie);
+set!(0x104, __set_sie);
+clear!(0x104, __clear_sie);
 
 /// User Software Interrupt Enable
 set_clear_csr!(set_usoft, clear_usoft, 1 << 0);
diff --git a/src/register/sip.rs b/src/register/sip.rs
index bd419e7..f625661 100644
--- a/src/register/sip.rs
+++ b/src/register/sip.rs
@@ -52,4 +52,4 @@ impl Sip {
     }
 }
 
-read_csr_as!(Sip, 0x144);
+read_csr_as!(Sip, 0x144, __read_sip);
diff --git a/src/register/sscratch.rs b/src/register/sscratch.rs
index d910d6e..349812c 100644
--- a/src/register/sscratch.rs
+++ b/src/register/sscratch.rs
@@ -1,4 +1,4 @@
 //! sscratch register
 
-read_csr_as_usize!(0x140);
-write_csr_as_usize!(0x140);
+read_csr_as_usize!(0x140, __read_sscratch);
+write_csr_as_usize!(0x140, __write_sscratch);
diff --git a/src/register/sstatus.rs b/src/register/sstatus.rs
index ee11533..455d405 100644
--- a/src/register/sstatus.rs
+++ b/src/register/sstatus.rs
@@ -104,9 +104,9 @@ impl Sstatus {
     }
 }
 
-read_csr_as!(Sstatus, 0x100);
-set!(0x100);
-clear!(0x100);
+read_csr_as!(Sstatus, 0x100, __read_sstatus);
+set!(0x100, __set_sstatus);
+clear!(0x100, __clear_sstatus);
 
 /// User Interrupt Enable
 set_clear_csr!(set_uie, clear_uie, 1 << 0);
diff --git a/src/register/stval.rs b/src/register/stval.rs
index fb37ee9..722cc19 100644
--- a/src/register/stval.rs
+++ b/src/register/stval.rs
@@ -1,3 +1,3 @@
 //! stval register
 
-read_csr_as_usize!(0x143);
+read_csr_as_usize!(0x143, __read_stval);
diff --git a/src/register/stvec.rs b/src/register/stvec.rs
index d780795..5a179d0 100644
--- a/src/register/stvec.rs
+++ b/src/register/stvec.rs
@@ -34,8 +34,8 @@ impl Stvec {
     }
 }
 
-read_csr_as!(Stvec, 0x105);
-write_csr!(0x105);
+read_csr_as!(Stvec, 0x105, __read_stvec);
+write_csr!(0x105, __write_stvec);
 
 /// Writes the CSR
 #[inline]
diff --git a/src/register/time.rs b/src/register/time.rs
index e626742..8793475 100644
--- a/src/register/time.rs
+++ b/src/register/time.rs
@@ -1,3 +1,3 @@
 //! time register
 
-read_csr_as_usize!(0xC01);
+read_csr_as_usize!(0xC01, __read_time);
diff --git a/src/register/timeh.rs b/src/register/timeh.rs
index 884c9ab..ff725db 100644
--- a/src/register/timeh.rs
+++ b/src/register/timeh.rs
@@ -1,3 +1,3 @@
 //! timeh register
 
-read_csr_as_usize_rv32!(0xC81);
+read_csr_as_usize_rv32!(0xC81, __read_timeh);