Merge #22

22: Update CI, add MSRV policy r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

.travis.yml

@@ -1,29 +1,18 @@
 language: rust
 
+env:
+  - TARGET=x86_64-unknown-linux-gnu
+  - TARGET=riscv32imac-unknown-none-elf
+
+rust:
+  - nightly
+  - stable
+  - 1.30.0 # MSRV
+
+if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
 matrix:
   include:
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
     - env: TARGET=riscv64imac-unknown-none-elf
       rust: nightly
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
@@ -32,26 +21,23 @@ matrix:
       rust: nightly
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: stable
+    - env: CHECK_BLOBS=1
+      rust:
+      language: bash
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-before_install: set -e
 
 install:
-  - bash ci/install.sh
-  - export PATH="$PATH:$PWD/gcc/bin"
+  - ci/install.sh
 
 script:
-  - bash ci/script.sh
+  - ci/script.sh
 
-after_script: set +e
 
-cache: cargo
+cache:
+  cargo: true
+  directories:
+    - gcc
 before_cache:
   # Travis can't cache files that are not readable by "others"
   - chmod -R a+r $HOME/.cargo

ci/install.sh

@@ -1,12 +1,14 @@
+#!/usr/bin/env bash
+
 set -euxo pipefail
 
-main() {
-    if [ $TARGET != x86_64-unknown-linux-gnu ]; then
+if [ -n "${TARGET:-}" ]; then
     rustup target add $TARGET
-    fi
+fi
 
-    mkdir gcc
+if [ -n "${CHECK_BLOBS:-}" ]; then
+    if [ ! -d gcc/bin ]; then
+        mkdir -p gcc
         curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
-}
-
-main
+    fi
+fi

ci/script.sh

@@ -1,15 +1,16 @@
+#!/usr/bin/env bash
+
 set -euxo pipefail
 
-main() {
+if [ -n "${TARGET:-}" ]; then
     cargo check --target $TARGET
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
         cargo check --target $TARGET --features inline-asm
     fi
+fi
 
-    if [ $TARGET = x86_64-unknown-linux-gnu ]; then
+if [ -n "${CHECK_BLOBS:-}" ]; then
+    PATH="$PATH:$PWD/gcc/bin"
     ./check-blobs.sh
-    fi
-}
-
-main
+fi

src/lib.rs

@@ -1,8 +1,17 @@
 //! Low level access to RISC-V processors
 //!
+//! # Minimum Supported Rust Version (MSRV)
+//!
+//! This crate is guaranteed to compile on stable Rust 1.30 and up. It *might*
+//! compile with older versions but that may change in any new patch release.
+//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
+//! are not supported on stable yet.
+//!
+//! # Features
+//!
 //! This crate provides:
 //!
-//! - Access to core registers like mstatus or mcause.
+//! - Access to core registers like `mstatus` or `mcause`.
 //! - Interrupt manipulation mechanisms.
 //! - Wrappers around assembly instructions like `WFI`.