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Merge #34 

34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift

Per the RISC-V privileged ISA, these registers should be writable.

Co-authored-by: Gui Andrade <gh@archshift.com>
This commit is contained in:
bors[bot] 2019-10-10 07:32:26 +00:00 committed by GitHub
parent 0eda3c511c 7a9aa062a0
commit 0259333c75
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 28 additions and 1 deletions
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27
src/register/mip.rs
View File

@ -71,3 +71,30 @@ impl Mip {
} }
read_csr_as!(Mip, 0x344, __read_mip); read_csr_as!(Mip, 0x344, __read_mip);
set!(0x344, __set_mip);
clear!(0x344, __clear_mip);
set_clear_csr!(
/// User Software Interrupt Pending
, set_usoft, clear_usoft, 1 << 0);
set_clear_csr!(
/// Supervisor Software Interrupt Pending
, set_ssoft, clear_ssoft, 1 << 1);
set_clear_csr!(
/// Machine Software Interrupt Pending
, set_msoft, clear_msoft, 1 << 3);
set_clear_csr!(
/// User Timer Interrupt Pending
, set_utimer, clear_utimer, 1 << 4);
set_clear_csr!(
/// Supervisor Timer Interrupt Pending
, set_stimer, clear_stimer, 1 << 5);
set_clear_csr!(
/// Machine Timer Interrupt Pending
, set_mtimer, clear_mtimer, 1 << 7);
set_clear_csr!(
/// User External Interrupt Pending
, set_uext, clear_uext, 1 << 8);
set_clear_csr!(
/// Supervisor External Interrupt Pending
, set_sext, clear_sext, 1 << 9);

2
src/register/satp.rs
View File

@ -87,7 +87,7 @@ pub enum Mode {
} }
read_csr_as!(Satp, 0x180, __read_satp); read_csr_as!(Satp, 0x180, __read_satp);
write_csr!(0x180, __write_satp); write_csr_as_usize!(0x180, __write_satp);
#[inline] #[inline]
#[cfg(riscv32)] #[cfg(riscv32)]