diff --git a/src/main.rs b/src/main.rs
index 1302f0a..383457a 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -73,10 +73,10 @@ fn main() -> ! {
     stm32_eth::setup(&dp.RCC, &dp.SYSCFG);
     let clocks = dp.RCC.constrain()
         .cfgr
-        .sysclk(84.mhz())
-        .hclk(84.mhz())
-        .pclk1(16.mhz())
-        .pclk2(32.mhz())
+        .sysclk(168.mhz())
+        .hclk(168.mhz())
+        .pclk1(32.mhz())
+        .pclk2(64.mhz())
         .freeze();
 
     let mut wd = IndependentWatchdog::new(dp.IWDG);
diff --git a/src/timer.rs b/src/timer.rs
index 98e3505..7d57d28 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -9,7 +9,7 @@ use stm32f4xx_hal::{
 };
 
 /// Rate in Hz
-const TIMER_RATE: u32 = 10;
+const TIMER_RATE: u32 = 20;
 /// Interval duration in milliseconds
 const TIMER_DELTA: u32 = 1000 / TIMER_RATE;
 /// Elapsed time in milliseconds