setup clocks to 168 mhz, adjust TIMER_RATE to 20

systick must elapse more often at higher clock.
master
Astro 2019-03-18 22:04:34 +01:00
parent 58ac89b66e
commit 3f6bb05001
2 changed files with 5 additions and 5 deletions

View File

@ -73,10 +73,10 @@ fn main() -> ! {
stm32_eth::setup(&dp.RCC, &dp.SYSCFG);
let clocks = dp.RCC.constrain()
.cfgr
.sysclk(84.mhz())
.hclk(84.mhz())
.pclk1(16.mhz())
.pclk2(32.mhz())
.sysclk(168.mhz())
.hclk(168.mhz())
.pclk1(32.mhz())
.pclk2(64.mhz())
.freeze();
let mut wd = IndependentWatchdog::new(dp.IWDG);

View File

@ -9,7 +9,7 @@ use stm32f4xx_hal::{
};
/// Rate in Hz
const TIMER_RATE: u32 = 10;
const TIMER_RATE: u32 = 20;
/// Interval duration in milliseconds
const TIMER_DELTA: u32 = 1000 / TIMER_RATE;
/// Elapsed time in milliseconds