@@ -180,6 +180,10 @@ postfilter rate can be tuned with the `postfilter` command.
 - Connect Peliter device 1 to TEC1- and TEC1+.
 - The GND pin is for shielding not for sinking Peltier currents.
 
+When using a TEC module with the Thermostat, the Thermostat expects the thermal load (where the thermistor is located) to heat up with a positive software current set point, and cool down with a negative current set point.

@@ -114,3 +112,2 @@
-        };
         let voltage = self.channel_state(channel).dac_value;
-        let max = ElectricPotential::new::<volt>(ad5680::MAX_VALUE as f64 / dac_factor);
+        let max = ElectricPotential::new::<volt>(DAC_OUT_MAX_V);

@@ -23,2 +23,4 @@
 pub const CHANNELS: usize = 2;
 pub const R_SENSE: f64 = 0.05;
+// DAC chip outputs 0-5v, which is then passed through a resistor dividor to provide 0-3v range
+pub const DAC_OUT_MAX_V: f64 = 3.0;

@@ -260,7 +256,12 @@ impl Channels {
     /// These loops perform a breadth-first search for the DAC setting
     /// that will produce a `target_voltage`.

@@ -348,3 +349,2 @@
     pub fn get_max_v(&mut self, channel: usize) -> (ElectricPotential, ElectricPotential) {
-        let vref = self.channel_state(channel).vref;
-        let max = 4.0 * vref;
+        let max = 4.0 * ElectricPotential::new::<volt>(3.3);

@@ -263,1 +259,3 @@
-        let target_voltage = ElectricPotential::new::<volt>(2.5);
+        let samples = 50;
+        let mut target_voltage = ElectricPotential::new::<volt>(0.0);
+        for _ in (0..samples).rev() {

@@ -260,7 +256,12 @@ impl Channels {
     /// These loops perform a breadth-first search for the DAC setting

@@ -153,3 +149,2 @@
         let i_tec = (voltage - center_point) / (10.0 * r_sense);
-        let max = (max - center_point) / (10.0 * r_sense);
-        (i_tec, max)
+        // let max = (max - center_point) / (10.0 * r_sense);

@@ -262,0 +256,4 @@
+    /// The thermostat DAC applies a control voltage signal to the CTLI pin of MAX driver chip to control output current.
+    /// The CTLI input signal is centered around VREF of the MAX chip. Applying VREF to CTLI sets the output current to 0.
+    /// 
+    /// This calibration routine reads the VREF voltage, and finds a DAC output value that would 

@@ -1,6 +1,6 @@
 #![cfg_attr(not(test), no_std)]
 #![cfg_attr(not(test), no_main)]
-#![feature(maybe_uninit_extra, maybe_uninit_ref, asm)]
+#![feature(maybe_uninit_extra, maybe_uninit_ref, asm, const_fn)]

@@ -1,4 +1,8 @@
 use stm32f4xx_hal::hal::digital::v2::OutputPin;
+use uom::si::{
+    f64::{ElectricPotential},