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1 Commits
Author | SHA1 | Date |
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Astro | f323c1be63 |
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@ -358,6 +358,7 @@ dependencies = [
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"cortex-m-rt",
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"hash2hwaddr",
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"log",
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"nb",
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"nom",
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"num-traits",
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"panic-abort",
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@ -29,6 +29,7 @@ bit_field = "0.10"
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byteorder = { version = "1", default-features = false }
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nom = { version = "5", default-features = false }
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num-traits = { version = "0.2", default-features = false, features = ["libm"] }
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nb = "0.1"
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[patch.crates-io]
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# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
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@ -32,6 +32,7 @@ mod init_log;
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use init_log::init_log;
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mod pins;
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use pins::Pins;
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mod softspi;
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mod ad7172;
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mod ad5680;
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mod net;
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@ -89,6 +90,8 @@ fn main() -> ! {
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wd.start(WATCHDOG_INTERVAL.ms());
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wd.feed();
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timer::setup(cp.SYST, clocks);
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let pins = Pins::setup(
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clocks, dp.TIM1, dp.TIM3,
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dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG,
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@ -98,8 +101,6 @@ fn main() -> ! {
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let mut channels = Channels::new(pins);
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channels.calibrate_dac_value(0);
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timer::setup(cp.SYST, clocks);
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#[cfg(not(feature = "generate-hwaddr"))]
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let hwaddr = EthernetAddress(NET_HWADDR);
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#[cfg(feature = "generate-hwaddr")]
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44
src/pins.rs
44
src/pins.rs
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@ -1,6 +1,6 @@
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use stm32f4xx_hal::{
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adc::Adc,
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hal::{blocking::spi::Transfer, digital::v2::OutputPin},
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hal::{blocking::spi::Transfer, digital::v2::{InputPin, OutputPin}},
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gpio::{
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AF5, Alternate, Analog,
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gpioa::*,
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@ -20,6 +20,20 @@ use stm32f4xx_hal::{
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time::U32Ext,
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};
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use crate::channel::{Channel0, Channel1};
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use crate::softspi::SoftSpi;
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pub struct DummyInputPin;
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impl InputPin for DummyInputPin {
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type Error = (); // `Void`
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fn is_high(&self) -> Result<bool, Self::Error> {
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Ok(false)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(true)
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}
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}
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pub trait ChannelPins {
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@ -58,8 +72,8 @@ impl ChannelPins for Channel1 {
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/// SPI peripheral used for communication with the ADC
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pub type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Alternate<AF5>>)>;
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pub type AdcNss = PB12<Output<PushPull>>;
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type Dac0Spi = Spi<SPI4, (PE2<Alternate<AF5>>, NoMiso, PE6<Alternate<AF5>>)>;
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type Dac1Spi = Spi<SPI5, (PF7<Alternate<AF5>>, NoMiso, PF9<Alternate<AF5>>)>;
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type Dac0Spi = SoftSpi<PE2<Output<PushPull>>, PE6<Output<PushPull>>, DummyInputPin>;
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type Dac1Spi = SoftSpi<PF7<Output<PushPull>>, PF9<Output<PushPull>>, DummyInputPin>;
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pub type TecUMeasAdc = Adc<ADC3>;
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@ -196,14 +210,10 @@ impl Pins {
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clocks: Clocks, spi4: SPI4,
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sclk: PE2<M1>, sync: PE4<M2>, sdin: PE6<M3>
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) -> (Dac0Spi, PE4<Output<PushPull>>) {
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let sclk = sclk.into_alternate_af5();
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let sdin = sdin.into_alternate_af5();
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let spi = Spi::spi4(
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spi4,
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(sclk, NoMiso, sdin),
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crate::ad5680::SPI_MODE,
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crate::ad5680::SPI_CLOCK.into(),
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clocks
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let sclk = sclk.into_push_pull_output();
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let sdin = sdin.into_push_pull_output();
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let spi = SoftSpi::new(
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sclk, sdin, DummyInputPin,
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);
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let sync = sync.into_push_pull_output();
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@ -214,14 +224,10 @@ impl Pins {
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clocks: Clocks, spi5: SPI5,
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sclk: PF7<M1>, sync: PF6<M2>, sdin: PF9<M3>
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) -> (Dac1Spi, PF6<Output<PushPull>>) {
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let sclk = sclk.into_alternate_af5();
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let sdin = sdin.into_alternate_af5();
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let spi = Spi::spi5(
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spi5,
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(sclk, NoMiso, sdin),
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crate::ad5680::SPI_MODE,
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crate::ad5680::SPI_CLOCK.into(),
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clocks
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let sclk = sclk.into_push_pull_output();
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let sdin = sdin.into_push_pull_output();
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let spi = SoftSpi::new(
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sclk, sdin, DummyInputPin,
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);
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let sync = sync.into_push_pull_output();
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@ -0,0 +1,147 @@
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use stm32f4xx_hal::hal::{
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spi::FullDuplex,
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digital::v2::{InputPin, OutputPin},
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blocking::spi::{Transfer, transfer},
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};
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use nb::{block, Error, Error::WouldBlock};
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use crate::timer::now;
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/// Bit-banged Mode3 SPI
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pub struct SoftSpi<SCK, MOSI, MISO> {
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sck: SCK,
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mosi: MOSI,
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miso: MISO,
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state: State,
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input: Option<u8>,
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}
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#[derive(PartialEq)]
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enum State {
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Idle,
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Transfer {
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clock_phase: bool,
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mask: u8,
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output: u8,
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input: u8,
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},
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}
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impl<SCK: OutputPin, MOSI: OutputPin, MISO: InputPin> SoftSpi<SCK, MOSI, MISO> {
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pub fn new(mut sck: SCK, mut mosi: MOSI, miso: MISO) -> Self {
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let _ = sck.set_high();
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let _ = mosi.set_low();
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SoftSpi {
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sck, mosi, miso,
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state: State::Idle,
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input: None,
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}
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}
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/// Call this at twice the data rate
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pub fn tick(&mut self) {
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match self.state {
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State::Idle => {}
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State::Transfer { clock_phase: false,
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mask, output, input } => {
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if output & mask != 0 {
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let _ = self.mosi.set_high();
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} else {
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let _ = self.mosi.set_low();
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}
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let _ = self.sck.set_low();
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self.state = State::Transfer {
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clock_phase: true,
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mask, output, input,
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};
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}
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State::Transfer { clock_phase: true,
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mask, output, mut input } => {
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if self.miso.is_high().unwrap_or(false) {
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input |= mask;
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}
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let _ = self.sck.set_high();
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if mask != 1 {
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self.state = State::Transfer {
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clock_phase: false,
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mask: mask >> 1,
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output, input,
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};
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} else {
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self.input = Some(input);
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self.state = State::Idle;
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}
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}
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}
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}
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pub fn run(&mut self) {
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while self.state != State::Idle {
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self.tick();
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spi_delay();
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}
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}
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fn retry<R, E, F>(&mut self, f: &F) -> Result<R, E>
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where
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F: Fn(&'_ mut SoftSpi<SCK, MOSI, MISO>) -> Result<R, nb::Error<E>>
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{
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loop {
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match f(self) {
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Ok(r) => return Ok(r),
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Err(nb::Error::Other(e)) => return Err(e),
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Err(WouldBlock) => self.run(),
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}
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}
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}
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}
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impl<SCK: OutputPin, MOSI: OutputPin, MISO: InputPin> FullDuplex<u8> for SoftSpi<SCK, MOSI, MISO> {
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type Error = ();
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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match self.input.take() {
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Some(input) =>
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Ok(input),
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None if self.state == State::Idle =>
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Err(nb::Error::Other(())),
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None =>
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Err(WouldBlock),
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}
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}
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fn send(&mut self, output: u8) -> Result<(), nb::Error<Self::Error>> {
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match self.state {
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State::Idle => {
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self.state = State::Transfer {
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clock_phase: false,
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mask: 0x80,
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output,
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input: 0,
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};
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Ok(())
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}
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_ => Err(WouldBlock)
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}
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}
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}
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impl<SCK: OutputPin, MOSI: OutputPin, MISO: InputPin> Transfer<u8> for SoftSpi<SCK, MOSI, MISO> {
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// TODO: proper type
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type Error = ();
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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for b in words.iter_mut() {
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self.retry(&|spi| spi.send(*b))?;
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*b = self.retry(&|spi| spi.read())?;
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}
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Ok(words)
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}
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}
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fn spi_delay() {
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const DELAY: u32 = 1;
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let start = now();
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while now() - start < DELAY {}
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}
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