clock speed changed, pending correponding SPI changes

src/main.rs

@@ -107,8 +107,8 @@ fn main() -> ! {
         .use_hse(HSE)
         .sysclk(168.mhz())
         .hclk(168.mhz())
-        .pclk1(32.mhz())
-        .pclk2(64.mhz())
+        .pclk1(42.mhz())
+        .pclk2(84.mhz())
         .freeze();
 
     let mut wd = IndependentWatchdog::new(dp.IWDG);