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No commits in common. "f9b55508dd6e22fa550faf1be9098e6e4691e86c" and "3c943424481a587fa8a0b65d5e6c1a407b9b3e86" have entirely different histories.

3 changed files with 8 additions and 17 deletions

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@ -6,7 +6,6 @@ use stm32f4xx_hal::{
time::MegaHertz,
spi,
};
use crate::timer::sleep;
/// SPI Mode 1
pub const SPI_MODE: spi::Mode = spi::Mode {
@ -34,23 +33,23 @@ impl<SPI: Transfer<u8>, S: OutputPin> Dac<SPI, S> {
}
}
fn write(&mut self, buf: &mut [u8]) -> Result<(), SPI::Error> {
fn write(&mut self, mut buf: [u8; 3]) -> Result<(), SPI::Error> {
// pulse sync to start a new transfer. leave sync idle low
// afterwards to save power as recommended per datasheet.
let _ = self.sync.set_high();
// must be high for >= 33 ns
sleep(1);
cortex_m::asm::nop();
let _ = self.sync.set_low();
self.spi.transfer(buf)?;
self.spi.transfer(&mut buf)?;
Ok(())
}
pub fn set(&mut self, value: u32) -> Result<(), SPI::Error> {
let mut buf = [
let buf = [
(value >> 14) as u8,
(value >> 6) as u8,
(value << 2) as u8,
];
self.write(&mut buf)
self.write(buf)
}
}

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@ -89,17 +89,16 @@ fn main() -> ! {
wd.start(WATCHDOG_INTERVAL.ms());
wd.feed();
timer::setup(cp.SYST, clocks);
let pins = Pins::setup(
clocks, dp.TIM1, dp.TIM3,
dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG,
dp.SPI2, dp.SPI4, dp.SPI5,
dp.ADC1,
dp.ADC1, dp.ADC2, dp.ADC3,
);
let mut channels = Channels::new(pins);
channels.calibrate_dac_value(0);
timer::setup(cp.SYST, clocks);
#[cfg(not(feature = "generate-hwaddr"))]
let hwaddr = EthernetAddress(NET_HWADDR);

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@ -39,10 +39,3 @@ pub fn now() -> u32 {
.deref()
})
}
/// block for at least `amount` milliseconds
fn sleep(amount: u32) {
use crate::timer::now;
let start = now();
while now() - start <= amount {}
}