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No commits in common. "d203f21caf91c9adc78f065a887eabc2f9e78ed8" and "a102e5fcecdeee2fc57a30f777e6a3fe3702af93" have entirely different histories.

6 changed files with 40 additions and 67 deletions

1
Cargo.lock generated
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@ -355,6 +355,7 @@ dependencies = [
"cortex-m", "cortex-m",
"cortex-m-log", "cortex-m-log",
"cortex-m-rt", "cortex-m-rt",
"embedded-hal",
"hash2hwaddr", "hash2hwaddr",
"log", "log",
"nom", "nom",

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@ -21,6 +21,7 @@ bare-metal = "0.2"
cortex-m = "0.6" cortex-m = "0.6"
cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-rt = { version = "0.6", features = ["device"] }
cortex-m-log = { version = "0.6", features = ["log-integration"] } cortex-m-log = { version = "0.6", features = ["log-integration"] }
embedded-hal = "0.2"
# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125 # TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl", features = ["rt", "stm32f427"] } stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl", features = ["rt", "stm32f427"] }
stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" } stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }

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@ -1,8 +1,8 @@
use embedded_hal::{
blocking::spi::Transfer,
digital::v2::OutputPin,
};
use stm32f4xx_hal::{ use stm32f4xx_hal::{
hal::{
blocking::spi::Transfer,
digital::v2::OutputPin,
},
time::MegaHertz, time::MegaHertz,
spi, spi,
}; };

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@ -1,9 +1,7 @@
use core::fmt; use core::fmt;
use embedded_hal::digital::v2::OutputPin;
use embedded_hal::blocking::spi::Transfer;
use log::{info, warn}; use log::{info, warn};
use stm32f4xx_hal::hal::{
blocking::spi::Transfer,
digital::v2::OutputPin,
};
use super::{ use super::{
regs::{self, Register, RegisterData}, regs::{self, Register, RegisterData},
checksum::{ChecksumMode, Checksum}, checksum::{ChecksumMode, Checksum},
@ -186,9 +184,8 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
let checksum_out = checksum.result(); let checksum_out = checksum.result();
let mut data = reg_data.clone(); let mut data = reg_data.clone();
self.transfer(address, data.as_mut(), checksum_out)?; let checksum_in = self.transfer(address, data.as_mut(), checksum_out)?;
// Verification
let readback_data = self.read_reg(reg)?; let readback_data = self.read_reg(reg)?;
if *readback_data == **reg_data { if *readback_data == **reg_data {
return Ok(()); return Ok(());

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@ -16,7 +16,6 @@ use cortex_m_rt::entry;
use stm32f4xx_hal::{ use stm32f4xx_hal::{
hal::{ hal::{
self, self,
digital::v2::OutputPin,
watchdog::{WatchdogEnable, Watchdog}, watchdog::{WatchdogEnable, Watchdog},
}, },
rcc::RccExt, rcc::RccExt,
@ -93,21 +92,14 @@ fn main() -> ! {
); );
let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap(); let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
// Feature not used
adc.set_sync_enable(false).unwrap();
// Setup channels
adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap(); adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap(); adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
adc.calibrate_offset().unwrap(); adc.calibrate_offset().unwrap();
let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync); let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync);
dac0.set(0).unwrap(); dac0.set(0).unwrap();
let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync); let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync);
dac1.set(0).unwrap(); dac1.set(0).unwrap();
let mut pwm = pins.pwm; let mut pwm = pins.pwm;
let mut shdn0 = pins.shdn0;
let mut shdn1 = pins.shdn1;
timer::setup(cp.SYST, clocks); timer::setup(cp.SYST, clocks);
@ -127,6 +119,13 @@ fn main() -> ! {
net::run(dp.ETHERNET_MAC, dp.ETHERNET_DMA, hwaddr, |iface| { net::run(dp.ETHERNET_MAC, dp.ETHERNET_DMA, hwaddr, |iface| {
Server::<Session>::run(iface, |server| { Server::<Session>::run(iface, |server| {
loop { loop {
let instant = Instant::from_millis(i64::from(timer::now()));
cortex_m::interrupt::free(net::clear_pending);
server.poll(instant)
.unwrap_or_else(|e| {
warn!("poll: {:?}", e);
});
let instant = Instant::from_millis(i64::from(timer::now())); let instant = Instant::from_millis(i64::from(timer::now()));
// ADC input // ADC input
adc.data_ready().unwrap().map(|channel| { adc.data_ready().unwrap().map(|channel| {
@ -138,14 +137,10 @@ fn main() -> ! {
if state.pid_enabled { if state.pid_enabled {
// Forward PID output to i_set DAC // Forward PID output to i_set DAC
match channel { match channel {
0 => { 0 =>
dac0.set(state.dac_value).unwrap(); dac0.set(state.dac_value).unwrap(),
shdn0.set_high().unwrap(); 1 =>
} dac1.set(state.dac_value).unwrap(),
1 => {
dac1.set(state.dac_value).unwrap();
shdn1.set_high().unwrap();
}
_ => _ =>
unreachable!(), unreachable!(),
} }
@ -154,16 +149,9 @@ fn main() -> ! {
server.for_each(|_, session| session.set_report_pending(channel.into())); server.for_each(|_, session| session.set_report_pending(channel.into()));
}); });
let instant = Instant::from_millis(i64::from(timer::now()));
cortex_m::interrupt::free(net::clear_pending);
server.poll(instant)
.unwrap_or_else(|e| {
warn!("poll: {:?}", e);
});
// TCP protocol handling // TCP protocol handling
server.for_each(|mut socket, session| { server.for_each(|mut socket, session| {
if ! socket.is_active() { if ! socket.is_open() {
let _ = socket.listen(TCP_PORT); let _ = socket.listen(TCP_PORT);
session.reset(); session.reset();
} else if socket.can_send() && socket.can_recv() && socket.send_capacity() - socket.send_queue() > 1024 { } else if socket.can_send() && socket.can_recv() && socket.send_capacity() - socket.send_queue() > 1024 {
@ -287,14 +275,8 @@ fn main() -> ! {
Command::Pwm { channel, pin: PwmPin::ISet, duty } if duty <= ad5680::MAX_VALUE => { Command::Pwm { channel, pin: PwmPin::ISet, duty } if duty <= ad5680::MAX_VALUE => {
channel_states[channel].pid_enabled = false; channel_states[channel].pid_enabled = false;
match channel { match channel {
0 => { 0 => dac0.set(duty).unwrap(),
dac0.set(duty).unwrap(); 1 => dac1.set(duty).unwrap(),
shdn0.set_high().unwrap();
}
1 => {
dac1.set(duty).unwrap();
shdn1.set_high().unwrap();
}
_ => unreachable!(), _ => unreachable!(),
} }
channel_states[channel].dac_value = duty; channel_states[channel].dac_value = duty;
@ -420,13 +402,12 @@ fn main() -> ! {
// Update watchdog // Update watchdog
wd.feed(); wd.feed();
cortex_m::interrupt::free(|cs| { // cortex_m::interrupt::free(|cs| {
if !net::is_pending(cs) { // if !net::is_pending(cs) {
// Wait for interrupts // // Wait for interrupts
// (Ethernet or SysTick) // wfi();
wfi(); // }
} // });
});
} }
}); });
}); });

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@ -1,5 +1,4 @@
use stm32f4xx_hal::{ use stm32f4xx_hal::{
hal::digital::v2::OutputPin,
gpio::{ gpio::{
AF5, Alternate, AF5, Alternate,
gpioa::*, gpioa::*,
@ -31,10 +30,8 @@ pub struct Pins {
pub pwm: PwmPins, pub pwm: PwmPins,
pub dac0_spi: Dac0Spi, pub dac0_spi: Dac0Spi,
pub dac0_sync: PE4<Output<PushPull>>, pub dac0_sync: PE4<Output<PushPull>>,
pub shdn0: PE10<Output<PushPull>>,
pub dac1_spi: Dac1Spi, pub dac1_spi: Dac1Spi,
pub dac1_sync: PF6<Output<PushPull>>, pub dac1_sync: PF6<Output<PushPull>>,
pub shdn1: PE15<Output<PushPull>>,
} }
impl Pins { impl Pins {
@ -61,6 +58,15 @@ impl Pins {
let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15); let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
let adc_nss = gpiob.pb12.into_push_pull_output(); let adc_nss = gpiob.pb12.into_push_pull_output();
let (dac0_spi, dac0_sync) = Self::setup_dac0(
clocks, spi4,
gpioe.pe2, gpioe.pe4, gpioe.pe6
);
let (dac1_spi, dac1_sync) = Self::setup_dac1(
clocks, spi5,
gpiof.pf7, gpiof.pf6, gpiof.pf9
);
let pwm = PwmPins::setup( let pwm = PwmPins::setup(
clocks, tim1, tim3, clocks, tim1, tim3,
gpioc.pc6, gpioc.pc7, gpioc.pc6, gpioc.pc7,
@ -68,24 +74,11 @@ impl Pins {
gpioe.pe13, gpioe.pe14 gpioe.pe13, gpioe.pe14
); );
let (dac0_spi, dac0_sync) = Self::setup_dac0(
clocks, spi4,
gpioe.pe2, gpioe.pe4, gpioe.pe6
);
let mut shdn0 = gpioe.pe10.into_push_pull_output();
let _ = shdn0.set_low();
let (dac1_spi, dac1_sync) = Self::setup_dac1(
clocks, spi5,
gpiof.pf7, gpiof.pf6, gpiof.pf9
);
let mut shdn1 = gpioe.pe15.into_push_pull_output();
let _ = shdn1.set_low();
Pins { Pins {
adc_spi, adc_nss, adc_spi, adc_nss,
pwm, pwm,
dac0_spi, dac0_sync, shdn0, dac0_spi, dac0_sync,
dac1_spi, dac1_sync, shdn1, dac1_spi, dac1_sync,
} }
} }