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Author | SHA1 | Date |
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Astro | d203f21caf | |
Astro | 15f64358a2 | |
Astro | 7fe1d2f761 | |
Astro | dcf7babf32 | |
Astro | e7782c9cb3 | |
Astro | b345cc0865 |
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@ -355,7 +355,6 @@ dependencies = [
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"cortex-m",
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"cortex-m-log",
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"cortex-m-rt",
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"embedded-hal",
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"hash2hwaddr",
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"log",
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"nom",
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@ -21,7 +21,6 @@ bare-metal = "0.2"
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cortex-m = "0.6"
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-log = { version = "0.6", features = ["log-integration"] }
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embedded-hal = "0.2"
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# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
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stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl", features = ["rt", "stm32f427"] }
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stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
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@ -1,8 +1,8 @@
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use embedded_hal::{
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use stm32f4xx_hal::{
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hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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};
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use stm32f4xx_hal::{
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},
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time::MegaHertz,
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spi,
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};
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@ -1,7 +1,9 @@
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use core::fmt;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use log::{info, warn};
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use stm32f4xx_hal::hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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};
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use super::{
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regs::{self, Register, RegisterData},
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checksum::{ChecksumMode, Checksum},
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@ -184,8 +186,9 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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let checksum_out = checksum.result();
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let mut data = reg_data.clone();
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let checksum_in = self.transfer(address, data.as_mut(), checksum_out)?;
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self.transfer(address, data.as_mut(), checksum_out)?;
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// Verification
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let readback_data = self.read_reg(reg)?;
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if *readback_data == **reg_data {
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return Ok(());
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59
src/main.rs
59
src/main.rs
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@ -16,6 +16,7 @@ use cortex_m_rt::entry;
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use stm32f4xx_hal::{
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hal::{
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self,
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digital::v2::OutputPin,
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watchdog::{WatchdogEnable, Watchdog},
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},
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rcc::RccExt,
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@ -92,14 +93,21 @@ fn main() -> ! {
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);
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let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
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// Feature not used
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adc.set_sync_enable(false).unwrap();
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// Setup channels
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adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
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adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
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adc.calibrate_offset().unwrap();
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let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync);
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dac0.set(0).unwrap();
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let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync);
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dac1.set(0).unwrap();
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let mut pwm = pins.pwm;
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let mut shdn0 = pins.shdn0;
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let mut shdn1 = pins.shdn1;
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timer::setup(cp.SYST, clocks);
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@ -119,13 +127,6 @@ fn main() -> ! {
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net::run(dp.ETHERNET_MAC, dp.ETHERNET_DMA, hwaddr, |iface| {
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Server::<Session>::run(iface, |server| {
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loop {
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let instant = Instant::from_millis(i64::from(timer::now()));
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cortex_m::interrupt::free(net::clear_pending);
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server.poll(instant)
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.unwrap_or_else(|e| {
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warn!("poll: {:?}", e);
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});
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let instant = Instant::from_millis(i64::from(timer::now()));
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// ADC input
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adc.data_ready().unwrap().map(|channel| {
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@ -137,10 +138,14 @@ fn main() -> ! {
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if state.pid_enabled {
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// Forward PID output to i_set DAC
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match channel {
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0 =>
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dac0.set(state.dac_value).unwrap(),
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1 =>
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dac1.set(state.dac_value).unwrap(),
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0 => {
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dac0.set(state.dac_value).unwrap();
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shdn0.set_high().unwrap();
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}
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1 => {
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dac1.set(state.dac_value).unwrap();
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shdn1.set_high().unwrap();
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}
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_ =>
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unreachable!(),
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}
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@ -149,9 +154,16 @@ fn main() -> ! {
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server.for_each(|_, session| session.set_report_pending(channel.into()));
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});
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let instant = Instant::from_millis(i64::from(timer::now()));
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cortex_m::interrupt::free(net::clear_pending);
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server.poll(instant)
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.unwrap_or_else(|e| {
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warn!("poll: {:?}", e);
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});
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// TCP protocol handling
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server.for_each(|mut socket, session| {
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if ! socket.is_open() {
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if ! socket.is_active() {
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let _ = socket.listen(TCP_PORT);
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session.reset();
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} else if socket.can_send() && socket.can_recv() && socket.send_capacity() - socket.send_queue() > 1024 {
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@ -275,8 +287,14 @@ fn main() -> ! {
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Command::Pwm { channel, pin: PwmPin::ISet, duty } if duty <= ad5680::MAX_VALUE => {
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channel_states[channel].pid_enabled = false;
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match channel {
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0 => dac0.set(duty).unwrap(),
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1 => dac1.set(duty).unwrap(),
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0 => {
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dac0.set(duty).unwrap();
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shdn0.set_high().unwrap();
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}
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1 => {
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dac1.set(duty).unwrap();
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shdn1.set_high().unwrap();
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}
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_ => unreachable!(),
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}
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channel_states[channel].dac_value = duty;
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@ -402,12 +420,13 @@ fn main() -> ! {
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// Update watchdog
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wd.feed();
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// cortex_m::interrupt::free(|cs| {
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// if !net::is_pending(cs) {
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// // Wait for interrupts
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// wfi();
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// }
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// });
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cortex_m::interrupt::free(|cs| {
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if !net::is_pending(cs) {
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// Wait for interrupts
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// (Ethernet or SysTick)
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wfi();
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}
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});
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}
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});
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});
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29
src/pins.rs
29
src/pins.rs
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@ -1,4 +1,5 @@
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use stm32f4xx_hal::{
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hal::digital::v2::OutputPin,
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gpio::{
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AF5, Alternate,
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gpioa::*,
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@ -30,8 +31,10 @@ pub struct Pins {
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pub pwm: PwmPins,
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pub dac0_spi: Dac0Spi,
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pub dac0_sync: PE4<Output<PushPull>>,
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pub shdn0: PE10<Output<PushPull>>,
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pub dac1_spi: Dac1Spi,
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pub dac1_sync: PF6<Output<PushPull>>,
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pub shdn1: PE15<Output<PushPull>>,
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}
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impl Pins {
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@ -58,15 +61,6 @@ impl Pins {
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let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
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let adc_nss = gpiob.pb12.into_push_pull_output();
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let (dac0_spi, dac0_sync) = Self::setup_dac0(
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clocks, spi4,
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gpioe.pe2, gpioe.pe4, gpioe.pe6
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);
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let (dac1_spi, dac1_sync) = Self::setup_dac1(
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clocks, spi5,
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gpiof.pf7, gpiof.pf6, gpiof.pf9
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);
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let pwm = PwmPins::setup(
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clocks, tim1, tim3,
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gpioc.pc6, gpioc.pc7,
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@ -74,11 +68,24 @@ impl Pins {
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gpioe.pe13, gpioe.pe14
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);
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let (dac0_spi, dac0_sync) = Self::setup_dac0(
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clocks, spi4,
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gpioe.pe2, gpioe.pe4, gpioe.pe6
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);
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let mut shdn0 = gpioe.pe10.into_push_pull_output();
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let _ = shdn0.set_low();
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let (dac1_spi, dac1_sync) = Self::setup_dac1(
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clocks, spi5,
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gpiof.pf7, gpiof.pf6, gpiof.pf9
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);
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let mut shdn1 = gpioe.pe15.into_push_pull_output();
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let _ = shdn1.set_low();
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Pins {
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adc_spi, adc_nss,
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pwm,
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dac0_spi, dac0_sync,
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dac1_spi, dac1_sync,
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dac0_spi, dac0_sync, shdn0,
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dac1_spi, dac1_sync, shdn1,
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}
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}
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