ad7172: eliminate superfluous AdcError
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9c3485d05f
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da65ea21a4
@ -5,7 +5,7 @@ use log::{info, warn};
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use super::{
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regs::{self, Register, RegisterData},
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checksum::{ChecksumMode, Checksum},
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AdcError, Mode, Input, RefSource, PostFilter, DigitalFilterOrder,
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Mode, Input, RefSource, PostFilter, DigitalFilterOrder,
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};
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/// AD7172-2 implementation
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@ -18,7 +18,7 @@ pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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}
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impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, AdcError<SPI::Error>> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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@ -48,12 +48,12 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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}
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/// `0x00DX` for AD7172-2
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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pub fn identify(&mut self) -> Result<u16, SPI::Error> {
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self.read_reg(®s::Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), SPI::Error> {
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// Cannot use update_reg() here because checksum_mode is
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// updated between read_reg() and write_reg().
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let mut ifmode = self.read_reg(®s::IfMode)?;
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@ -63,7 +63,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), SPI::Error> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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@ -71,7 +71,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), AdcError<SPI::Error>> {
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) -> Result<(), SPI::Error> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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@ -95,7 +95,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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}
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/// Calibrates offset registers
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pub fn calibrate_offset(&mut self) -> Result<(), AdcError<SPI::Error>> {
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pub fn calibrate_offset(&mut self) -> Result<(), SPI::Error> {
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self.update_reg(®s::AdcMode, |adc_mode| {
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adc_mode.set_mode(Mode::SystemOffsetCalibration);
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})?;
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@ -108,7 +108,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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Ok(())
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}
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pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, AdcError<SPI::Error>> {
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pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, SPI::Error> {
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self.read_reg(®s::FiltCon { index })
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.map(|data| {
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if data.enh_filt_en() {
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@ -119,7 +119,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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})
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}
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pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), AdcError<SPI::Error>> {
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pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), SPI::Error> {
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self.update_reg(®s::FiltCon { index }, |data| {
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match filter {
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None => data.set_enh_filt_en(false),
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@ -132,7 +132,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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}
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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pub fn data_ready(&mut self) -> Result<Option<u8>, SPI::Error> {
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self.read_reg(®s::Status)
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.map(|status| {
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if status.ready() {
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@ -144,12 +144,12 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, AdcError<SPI::Error>> {
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pub fn read_data(&mut self) -> Result<u32, SPI::Error> {
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self.read_reg(®s::Data)
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.map(|data| data.data())
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}
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, SPI::Error> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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@ -170,7 +170,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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Ok(reg_data)
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}
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), SPI::Error> {
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loop {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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@ -194,7 +194,7 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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}
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, SPI::Error>
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where
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R: regs::Register,
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F: FnOnce(&mut R::Data) -> A,
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@ -21,19 +21,6 @@ pub const SPI_CLOCK: MegaHertz = MegaHertz(2);
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pub const MAX_VALUE: u32 = 0xFF_FFFF;
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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