Pins::setup, replace adc_input with ad7172
parent
71c1f8441c
commit
99f7f2b548
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@ -0,0 +1,212 @@
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use core::fmt;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use log::{info, warn};
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use super::checksum::{ChecksumMode, Checksum};
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use super::AdcError;
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use super::{
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regs, regs::RegisterData,
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Input, RefSource, PostFilter, DigitalFilterOrder,
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};
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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match adc.identify() {
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Err(e) =>
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warn!("Cannot identify ADC: {:?}", e),
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Ok(id) if id & 0xFFF0 == 0x00D0 =>
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info!("ADC id: {:04X}", id),
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Ok(id) =>
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info!("ADC id: {:04X} (corrupt)", id),
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}
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Ok(adc)
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}
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/// `0x00DX` for AD7172-2
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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self.read_reg(®s::Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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// Cannot use update_reg() here because checksum_mode is
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// updated between read_reg() and write_reg().
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let mut ifmode = self.read_reg(®s::IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(®s::IfMode, &mut ifmode)?;
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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}
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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data.set_refbuf_neg(true);
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data.set_ainbuf_pos(true);
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data.set_ainbuf_neg(true);
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data.set_ref_sel(RefSource::External);
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})?;
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_enh_filt_en(true);
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data.set_enh_filt(PostFilter::F16SPS);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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})?;
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// let mut offset = <regs::Offset as regs::Register>::Data::empty();
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// offset.set_offset(0);
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// self.write_reg(®s::Offset { index }, &mut offset);
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self.update_reg(®s::Channel { index }, |data| {
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data.set_setup(index);
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data.set_enabled(true);
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data.set_a_in_pos(in_pos);
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data.set_a_in_neg(in_neg);
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})?;
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Ok(())
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}
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pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, AdcError<SPI::Error>> {
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self.read_reg(®s::FiltCon { index })
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.map(|data| {
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if data.enh_filt_en() {
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Some(data.enh_filt())
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} else {
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None
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}
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})
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}
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pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::FiltCon { index }, |data| {
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match filter {
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None => data.set_enh_filt_en(false),
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Some(filter) => {
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data.set_enh_filt_en(true);
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data.set_enh_filt(filter);
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}
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}
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})
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}
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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self.read_reg(®s::Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<i32, AdcError<SPI::Error>> {
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self.read_reg(®s::Data)
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.map(|data| data.data())
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}
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(address);
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let checksum_out = checksum.result();
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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}
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Ok(reg_data)
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}
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(address);
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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where
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R: regs::Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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let _ = self.nss.set_low();
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let result = self.spi.transfer(&mut buf);
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = match self.spi.transfer(&mut addr_buf) {
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Ok(_) => self.spi.transfer(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_),None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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@ -0,0 +1,54 @@
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#[derive(Clone, Copy, PartialEq)]
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#[repr(u8)]
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pub enum ChecksumMode {
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Off = 0b00,
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/// Seems much less reliable than `Crc`
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Xor = 0b01,
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Crc = 0b10,
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}
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impl From<u8> for ChecksumMode {
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fn from(x: u8) -> Self {
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match x {
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0 => ChecksumMode::Off,
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1 => ChecksumMode::Xor,
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_ => ChecksumMode::Crc,
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}
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}
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}
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pub struct Checksum {
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mode: ChecksumMode,
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state: u8,
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}
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impl Checksum {
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pub fn new(mode: ChecksumMode) -> Self {
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Checksum { mode, state: 0 }
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}
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pub fn feed(&mut self, input: u8) {
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match self.mode {
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ChecksumMode::Off => {},
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ChecksumMode::Xor => self.state ^= input,
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ChecksumMode::Crc => {
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for i in 0..8 {
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let input_mask = 0x80 >> i;
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self.state = (self.state << 1) ^
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if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
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0x07 /* x8 + x2 + x + 1 */
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} else {
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0
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};
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}
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}
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}
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}
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pub fn result(&self) -> Option<u8> {
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match self.mode {
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ChecksumMode::Off => None,
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_ => Some(self.state)
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}
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}
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}
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@ -0,0 +1,210 @@
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use core::fmt;
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use stm32f4xx_hal::{
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time::{MegaHertz, U32Ext},
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spi,
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};
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pub mod regs;
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mod checksum;
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pub use checksum::ChecksumMode;
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mod adc;
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pub use adc::*;
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/// SPI Mode 3
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pub const SPI_MODE: spi::Mode = spi::Mode {
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polarity: spi::Polarity::IdleHigh,
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phase: spi::Phase::CaptureOnSecondTransition,
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};
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/// 2 MHz
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pub const SPI_CLOCK: MegaHertz = MegaHertz(2);
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum Input {
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Ain0 = 0,
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Ain1 = 1,
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Ain2 = 2,
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Ain3 = 3,
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Ain4 = 4,
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TemperaturePos = 17,
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TemperatureNeg = 18,
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AnalogSupplyPos = 19,
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AnalogSupplyNeg = 20,
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RefPos = 21,
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RefNeg = 22,
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Invalid = 0b11111,
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}
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impl From<u8> for Input {
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fn from(x: u8) -> Self {
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match x {
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0 => Input::Ain0,
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1 => Input::Ain1,
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2 => Input::Ain2,
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3 => Input::Ain3,
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4 => Input::Ain4,
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17 => Input::TemperaturePos,
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18 => Input::TemperatureNeg,
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19 => Input::AnalogSupplyPos,
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20 => Input::AnalogSupplyNeg,
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21 => Input::RefPos,
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22 => Input::RefNeg,
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_ => Input::Invalid,
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}
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}
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}
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impl fmt::Display for Input {
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fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
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use Input::*;
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match self {
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Ain0 => "ain0",
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Ain1 => "ain1",
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Ain2 => "ain2",
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Ain3 => "ain3",
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Ain4 => "ain4",
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TemperaturePos => "temperature+",
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TemperatureNeg => "temperature-",
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AnalogSupplyPos => "analogsupply+",
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AnalogSupplyNeg => "analogsupply-",
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RefPos => "ref+",
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RefNeg => "ref-",
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_ => "<INVALID>",
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}.fmt(fmt)
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}
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}
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/// Reference source for ADC conversion
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#[repr(u8)]
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pub enum RefSource {
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/// External reference
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External = 0b00,
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/// Internal 2.5V reference
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Internal = 0b10,
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/// AVDD1 − AVSS
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Avdd1MinusAvss = 0b11,
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Invalid = 0b01,
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}
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impl From<u8> for RefSource {
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fn from(x: u8) -> Self {
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match x {
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0 => RefSource::External,
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1 => RefSource::Internal,
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2 => RefSource::Avdd1MinusAvss,
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_ => RefSource::Invalid,
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}
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}
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}
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impl fmt::Display for RefSource {
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fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
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use RefSource::*;
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match self {
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External => "external",
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Internal => "internal",
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Avdd1MinusAvss => "avdd1-avss",
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_ => "<INVALID>",
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}.fmt(fmt)
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}
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}
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#[derive(Clone, Copy)]
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#[repr(u8)]
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pub enum PostFilter {
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/// 27 SPS, 47 dB rejection, 36.7 ms settling
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F27SPS = 0b010,
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/// 21.25 SPS, 62 dB rejection, 40 ms settling
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F21SPS = 0b011,
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/// 20 SPS, 86 dB rejection, 50 ms settling
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F20SPS = 0b101,
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/// 16.67 SPS, 92 dB rejection, 60 ms settling
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F16SPS = 0b110,
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Invalid = 0b111,
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}
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impl PostFilter {
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pub const VALID_VALUES: &'static [Self] = &[
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PostFilter::F27SPS,
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PostFilter::F21SPS,
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PostFilter::F20SPS,
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PostFilter::F16SPS,
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];
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pub fn closest(rate: f32) -> Option<Self> {
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/// (x - y).abs()
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fn d(x: f32, y: f32) -> f32 {
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if x >= y {
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x - y
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} else {
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y - x
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}
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}
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let mut best: Option<(f32, Self)> = None;
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for value in Self::VALID_VALUES {
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let error = d(rate, value.output_rate().unwrap());
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let better = best
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.map(|(best_error, _)| error < best_error)
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.unwrap_or(true);
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if better {
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best = Some((error, *value));
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}
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}
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best.map(|(_, best)| best)
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}
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/// Samples per Second
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pub fn output_rate(&self) -> Option<f32> {
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match self {
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PostFilter::F27SPS => Some(27.0),
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PostFilter::F21SPS => Some(21.25),
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PostFilter::F20SPS => Some(20.0),
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PostFilter::F16SPS => Some(16.67),
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PostFilter::Invalid => None,
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}
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}
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}
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impl From<u8> for PostFilter {
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fn from(x: u8) -> Self {
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match x {
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0b010 => PostFilter::F27SPS,
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0b011 => PostFilter::F21SPS,
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0b101 => PostFilter::F20SPS,
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0b110 => PostFilter::F16SPS,
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_ => PostFilter::Invalid,
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}
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}
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}
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#[repr(u8)]
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pub enum DigitalFilterOrder {
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Sinc5Sinc1 = 0b00,
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Sinc3 = 0b11,
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Invalid = 0b10,
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}
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impl From<u8> for DigitalFilterOrder {
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fn from(x: u8) -> Self {
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match x {
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0b00 => DigitalFilterOrder::Sinc5Sinc1,
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0b11 => DigitalFilterOrder::Sinc3,
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_ => DigitalFilterOrder::Invalid,
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}
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}
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}
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@ -0,0 +1,260 @@
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use byteorder::{BigEndian, ByteOrder};
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use bit_field::BitField;
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use super::*;
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pub trait Register {
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type Data: RegisterData;
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fn address(&self) -> u8;
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}
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pub trait RegisterData {
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fn empty() -> Self;
|
||||
fn as_mut(&mut self) -> &mut [u8];
|
||||
}
|
||||
|
||||
macro_rules! def_reg {
|
||||
($Reg: ident, $reg: ident, $addr: expr, $size: expr) => {
|
||||
/// AD7172 register
|
||||
pub struct $Reg;
|
||||
impl Register for $Reg {
|
||||
/// Register contents
|
||||
type Data = $reg::Data;
|
||||
/// Register address
|
||||
fn address(&self) -> u8 {
|
||||
$addr
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
/// Register contents
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
/// Generate zeroed register contents
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
/// Borrow for SPI transfer
|
||||
fn as_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
($Reg: ident, u8, $reg: ident, $addr: expr, $size: expr) => {
|
||||
pub struct $Reg { pub index: u8, }
|
||||
impl Register for $Reg {
|
||||
type Data = $reg::Data;
|
||||
fn address(&self) -> u8 {
|
||||
$addr + self.index
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
fn as_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! reg_bit {
|
||||
($getter: ident, $byte: expr, $bit: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> bool {
|
||||
self.0[$byte].get_bit($bit)
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bit: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> bool {
|
||||
self.0[$byte].get_bit($bit)
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: bool) {
|
||||
self.0[$byte].set_bit($bit, value);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! reg_bits {
|
||||
($getter: ident, $byte: expr, $bits: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> u8 {
|
||||
self.0[$byte].get_bits($bits)
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bits: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> u8 {
|
||||
self.0[$byte].get_bits($bits)
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: u8) {
|
||||
self.0[$byte].set_bits($bits, value);
|
||||
}
|
||||
};
|
||||
($getter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> $ty {
|
||||
self.0[$byte].get_bits($bits) as $ty
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> $ty {
|
||||
self.0[$byte].get_bits($bits).into()
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: $ty) {
|
||||
self.0[$byte].set_bits($bits, value as u8);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
def_reg!(Status, status, 0x00, 1);
|
||||
impl status::Data {
|
||||
/// Is there new data to read?
|
||||
pub fn ready(&self) -> bool {
|
||||
! self.not_ready()
|
||||
}
|
||||
|
||||
reg_bit!(not_ready, 0, 7, "No data ready indicator");
|
||||
reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
|
||||
reg_bit!(adc_error, 0, 6, "ADC error");
|
||||
reg_bit!(crc_error, 0, 5, "SPI CRC error");
|
||||
reg_bit!(reg_error, 0,4, "Register error");
|
||||
}
|
||||
|
||||
def_reg!(IfMode, if_mode, 0x02, 2);
|
||||
impl if_mode::Data {
|
||||
reg_bits!(crc, set_crc, 1, 2..=3, ChecksumMode, "SPI checksum mode");
|
||||
}
|
||||
|
||||
def_reg!(Data, data, 0x04, 3);
|
||||
impl data::Data {
|
||||
pub fn data(&self) -> i32 {
|
||||
let raw =
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2]);
|
||||
if raw & 0x80_0000 != 0 {
|
||||
((raw & 0x7F_FFFF) | 0x8000_0000) as i32
|
||||
} else {
|
||||
raw as i32
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(GpioCon, gpio_con, 0x06, 2);
|
||||
impl gpio_con::Data {
|
||||
reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
|
||||
}
|
||||
|
||||
def_reg!(Id, id, 0x07, 2);
|
||||
impl id::Data {
|
||||
pub fn id(&self) -> u16 {
|
||||
BigEndian::read_u16(&self.0)
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Channel, u8, channel, 0x10, 2);
|
||||
impl channel::Data {
|
||||
reg_bit!(enabled, set_enabled, 0, 7, "Channel enabled");
|
||||
reg_bits!(setup, set_setup, 0, 4..=5, "Setup number");
|
||||
|
||||
/// Which input is connected to positive input of this channel
|
||||
#[allow(unused)]
|
||||
pub fn a_in_pos(&self) -> Input {
|
||||
((self.0[0].get_bits(0..=1) << 3) |
|
||||
self.0[1].get_bits(5..=7)).into()
|
||||
}
|
||||
/// Set which input is connected to positive input of this channel
|
||||
#[allow(unused)]
|
||||
pub fn set_a_in_pos(&mut self, value: Input) {
|
||||
let value = value as u8;
|
||||
self.0[0].set_bits(0..=1, value >> 3);
|
||||
self.0[1].set_bits(5..=7, value & 0x7);
|
||||
}
|
||||
reg_bits!(a_in_neg, set_a_in_neg, 1, 0..=4, Input,
|
||||
"Which input is connected to negative input of this channel");
|
||||
|
||||
// const PROPS: &'static [Property<Self>] = &[
|
||||
// Property::named("enable")
|
||||
// .readable(&|self_: &Self| self_.enabled().into())
|
||||
// .writebale(&|self_: &mut Self, value| self_.set_enabled(value != 0)),
|
||||
// Property::named("setup")
|
||||
// .readable(&|self_: &Self| self_.0[0].get_bits(4..=5).into())
|
||||
// .writeable(&|self_: &mut Self, value| {
|
||||
// self_.0[0].set_bits(4..=5, value as u8);
|
||||
// }),
|
||||
// ];
|
||||
|
||||
// pub fn props() -> &'static [Property<Self>] {
|
||||
// Self::PROPS
|
||||
// }
|
||||
}
|
||||
|
||||
def_reg!(SetupCon, u8, setup_con, 0x20, 2);
|
||||
impl setup_con::Data {
|
||||
reg_bit!(bipolar, set_bipolar, 0, 4, "Unipolar (`false`) or bipolar (`true`) coded output");
|
||||
reg_bit!(refbuf_pos, set_refbuf_pos, 0, 3, "Enable REF+ input buffer");
|
||||
reg_bit!(refbuf_neg, set_refbuf_neg, 0, 2, "Enable REF- input buffer");
|
||||
reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 1, "Enable AIN+ input buffer");
|
||||
reg_bit!(ainbuf_neg, set_ainbuf_neg, 0, 0, "Enable AIN- input buffer");
|
||||
reg_bit!(burnout_en, 1, 7, "enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected");
|
||||
reg_bits!(ref_sel, set_ref_sel, 1, 4..=5, RefSource, "Select reference source for conversion");
|
||||
}
|
||||
|
||||
def_reg!(FiltCon, u8, filt_con, 0x28, 2);
|
||||
impl filt_con::Data {
|
||||
reg_bit!(sinc3_map, 0, 7, "If set, mapping of filter register changes to directly program the decimation rate of the sinc3 filter");
|
||||
reg_bit!(enh_filt_en, set_enh_filt_en, 0, 3, "Enable postfilters for enhanced 50Hz and 60Hz rejection");
|
||||
reg_bits!(enh_filt, set_enh_filt, 0, 0..=2, PostFilter, "Select postfilters for enhanced 50Hz and 60Hz rejection");
|
||||
reg_bits!(order, set_order, 1, 5..=6, DigitalFilterOrder, "order of the digital filter that processes the modulator data");
|
||||
reg_bits!(odr, set_odr, 1, 0..=4, "Output data rate");
|
||||
}
|
||||
|
||||
def_reg!(Offset, u8, offset, 0x30, 3);
|
||||
impl offset::Data {
|
||||
#[allow(unused)]
|
||||
pub fn offset(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
#[allow(unused)]
|
||||
pub fn set_offset(&mut self, value: u32) {
|
||||
self.0[0] = (value >> 16) as u8;
|
||||
self.0[1] = (value >> 8) as u8;
|
||||
self.0[2] = value as u8;
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Gain, u8, gain, 0x38, 3);
|
||||
impl gain::Data {
|
||||
#[allow(unused)]
|
||||
pub fn gain(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
#[allow(unused)]
|
||||
pub fn set_gain(&mut self, value: u32) {
|
||||
self.0[0] = (value >> 16) as u8;
|
||||
self.0[1] = (value >> 8) as u8;
|
||||
self.0[2] = value as u8;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
use stm32f4xx_hal::{
|
||||
adc::{
|
||||
Adc,
|
||||
config::*,
|
||||
},
|
||||
gpio::{Analog, gpioa::PA3 as Pin},
|
||||
stm32::ADC1 as ADC,
|
||||
};
|
||||
|
||||
/// ADC Input
|
||||
pub struct AdcInput {
|
||||
/// unused but consumed
|
||||
_pin: Pin<Analog>,
|
||||
adc: Adc<ADC>,
|
||||
}
|
||||
|
||||
impl AdcInput {
|
||||
/// Configure pin into analog mode
|
||||
pub fn new<MODE>(adc: ADC, pin: Pin<MODE>) -> Self {
|
||||
let pin = pin.into_analog();
|
||||
let adc_config = AdcConfig::default()
|
||||
.scan(Scan::Enabled)
|
||||
.continuous(Continuous::Single)
|
||||
.clock(Clock::Pclk2_div_2);
|
||||
let mut adc = Adc::adc1(adc, true, adc_config);
|
||||
|
||||
adc.configure_channel(&pin, Sequence::One, SampleTime::Cycles_480);
|
||||
|
||||
AdcInput { _pin: pin, adc }
|
||||
}
|
||||
|
||||
/// Enable the ADC,
|
||||
/// run a conversion
|
||||
/// disable the ADC
|
||||
pub fn read(&mut self) -> u16 {
|
||||
let adc = &mut self.adc;
|
||||
adc.enable();
|
||||
adc.clear_end_of_conversion_flag();
|
||||
adc.start_conversion();
|
||||
let sample = adc.current_sample();
|
||||
let result = adc.sample_to_millivolts(sample);
|
||||
adc.wait_for_conversion_sequence();
|
||||
adc.disable();
|
||||
result
|
||||
}
|
||||
}
|
||||
24
src/main.rs
24
src/main.rs
|
|
@ -15,7 +15,6 @@ use cortex_m_rt::entry;
|
|||
use embedded_hal::watchdog::{WatchdogEnable, Watchdog};
|
||||
use stm32f4xx_hal::{
|
||||
rcc::RccExt,
|
||||
gpio::GpioExt,
|
||||
watchdog::IndependentWatchdog,
|
||||
time::U32Ext,
|
||||
stm32::{CorePeripherals, Peripherals},
|
||||
|
|
@ -26,8 +25,8 @@ use smoltcp::{
|
|||
};
|
||||
|
||||
mod pins;
|
||||
mod adc_input;
|
||||
use adc_input::AdcInput;
|
||||
use pins::Pins;
|
||||
mod ad7172;
|
||||
mod net;
|
||||
mod server;
|
||||
use server::Server;
|
||||
|
|
@ -86,20 +85,11 @@ fn main() -> ! {
|
|||
wd.start(1000u32.ms());
|
||||
wd.feed();
|
||||
|
||||
let gpioa = dp.GPIOA.split();
|
||||
let gpiob = dp.GPIOB.split();
|
||||
let gpioc = dp.GPIOC.split();
|
||||
let gpiog = dp.GPIOG.split();
|
||||
let pins = Pins::setup(clocks, dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOG, dp.SPI2);
|
||||
|
||||
info!("ADC init");
|
||||
let mut adc_input = AdcInput::new(dp.ADC1, gpioa.pa3);
|
||||
|
||||
info!("Eth setup");
|
||||
pins::setup_ethernet(
|
||||
gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7,
|
||||
gpioc.pc4, gpioc.pc5, gpiob.pb11, gpiog.pg13,
|
||||
gpiob.pb13
|
||||
);
|
||||
let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
|
||||
adc.set_checksum_mode(ad7172::ChecksumMode::Crc).unwrap();
|
||||
|
||||
info!("Timer setup");
|
||||
timer::setup(cp.SYST, clocks);
|
||||
|
|
@ -128,8 +118,8 @@ fn main() -> ! {
|
|||
|
||||
let now = timer::now().0;
|
||||
if now - last_output >= OUTPUT_INTERVAL {
|
||||
let adc_value = adc_input.read();
|
||||
writeln!(server, "t={},pa3={}\r", now, adc_value).unwrap();
|
||||
// let adc_value = adc_input.read();
|
||||
writeln!(server, "t={},pa3={}\r", now, 0.0 /*adc_value*/).unwrap();
|
||||
last_output = now;
|
||||
}
|
||||
|
||||
|
|
|
|||
119
src/pins.rs
119
src/pins.rs
|
|
@ -1,32 +1,93 @@
|
|||
use stm32f4xx_hal::gpio::{
|
||||
gpioa::{PA1, PA2, PA7},
|
||||
gpiob::{PB11, PB13},
|
||||
gpioc::{PC1, PC4, PC5},
|
||||
gpiog::{PG13},
|
||||
Speed::VeryHigh,
|
||||
use stm32f4xx_hal::{
|
||||
gpio::{
|
||||
AF5, Alternate,
|
||||
gpioa::{PA1, PA2, PA7},
|
||||
gpiob::{PB10, PB11, PB12, PB13, PB14, PB15},
|
||||
gpioc::{PC1, PC4, PC5},
|
||||
gpiog::{PG13},
|
||||
GpioExt,
|
||||
Output, PushPull,
|
||||
Speed::VeryHigh,
|
||||
},
|
||||
rcc::Clocks,
|
||||
spi::Spi,
|
||||
stm32::{GPIOA, GPIOB, GPIOC, GPIOG, SPI2},
|
||||
};
|
||||
|
||||
pub fn setup_ethernet<M1, M2, M3, M4, M5, M6, M7, M8, M9>(
|
||||
pa1: PA1<M1>, pa2: PA2<M2>, pc1: PC1<M3>, pa7: PA7<M4>,
|
||||
pc4: PC4<M5>, pc5: PC5<M6>, pb11: PB11<M7>, pg13: PG13<M8>,
|
||||
pb13: PB13<M9>
|
||||
) {
|
||||
// PA1 RMII Reference Clock - SB13 ON
|
||||
pa1.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PA2 RMII MDIO - SB160 ON
|
||||
pa2.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC1 RMII MDC - SB164 ON
|
||||
pc1.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PA7 RMII RX Data Valid D11 JP6 ON
|
||||
pa7.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC4 RMII RXD0 - SB178 ON
|
||||
pc4.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC5 RMII RXD1 - SB181 ON
|
||||
pc5.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PB11 RMII TX Enable - SB183 ON
|
||||
pb11.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PG13 RXII TXD0 - SB182 ON
|
||||
pg13.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PB13 RMII TXD1 I2S_A_CK JP7 ON
|
||||
pb13.into_alternate_af11().set_speed(VeryHigh);
|
||||
|
||||
/// SPI peripheral used for communication with the ADC
|
||||
type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Alternate<AF5>>)>;
|
||||
|
||||
pub struct Pins {
|
||||
pub adc_spi: AdcSpi,
|
||||
pub adc_nss: PB12<Output<PushPull>>,
|
||||
}
|
||||
|
||||
impl Pins {
|
||||
/// Setup GPIO pins and configure MCU peripherals
|
||||
pub fn setup(clocks: Clocks, gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpiog: GPIOG, spi2: SPI2) -> Self {
|
||||
let gpioa = gpioa.split();
|
||||
let gpiob = gpiob.split();
|
||||
let gpioc = gpioc.split();
|
||||
let gpiog = gpiog.split();
|
||||
|
||||
Self::setup_ethernet(
|
||||
gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7,
|
||||
gpioc.pc4, gpioc.pc5, gpiob.pb11, gpiog.pg13,
|
||||
gpiob.pb13
|
||||
);
|
||||
let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
|
||||
let adc_nss = gpiob.pb12.into_push_pull_output();
|
||||
Pins {
|
||||
adc_spi,
|
||||
adc_nss,
|
||||
}
|
||||
}
|
||||
|
||||
/// Configure the GPIO pins for SPI operation, and initialize SPI
|
||||
fn setup_spi_adc<M1, M2, M3>(
|
||||
clocks: Clocks,
|
||||
spi2: SPI2,
|
||||
sck: PB10<M1>,
|
||||
miso: PB14<M2>,
|
||||
mosi: PB15<M3>,
|
||||
) -> AdcSpi
|
||||
{
|
||||
let sck = sck.into_alternate_af5();
|
||||
let miso = miso.into_alternate_af5();
|
||||
let mosi = mosi.into_alternate_af5();
|
||||
Spi::spi2(
|
||||
spi2,
|
||||
(sck, miso, mosi),
|
||||
crate::ad7172::SPI_MODE,
|
||||
crate::ad7172::SPI_CLOCK.into(),
|
||||
clocks
|
||||
)
|
||||
}
|
||||
|
||||
/// Configure the GPIO pins for Ethernet operation
|
||||
fn setup_ethernet<M1, M2, M3, M4, M5, M6, M7, M8, M9>(
|
||||
pa1: PA1<M1>, pa2: PA2<M2>, pc1: PC1<M3>, pa7: PA7<M4>,
|
||||
pc4: PC4<M5>, pc5: PC5<M6>, pb11: PB11<M7>, pg13: PG13<M8>,
|
||||
pb13: PB13<M9>
|
||||
) {
|
||||
// PA1 RMII Reference Clock - SB13 ON
|
||||
pa1.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PA2 RMII MDIO - SB160 ON
|
||||
pa2.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC1 RMII MDC - SB164 ON
|
||||
pc1.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PA7 RMII RX Data Valid D11 JP6 ON
|
||||
pa7.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC4 RMII RXD0 - SB178 ON
|
||||
pc4.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PC5 RMII RXD1 - SB181 ON
|
||||
pc5.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PB11 RMII TX Enable - SB183 ON
|
||||
pb11.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PG13 RXII TXD0 - SB182 ON
|
||||
pg13.into_alternate_af11().set_speed(VeryHigh);
|
||||
// PB13 RMII TXD1 I2S_A_CK JP7 ON
|
||||
pb13.into_alternate_af11().set_speed(VeryHigh);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue