add itec_pin
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a317eb60fd
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@ -14,8 +14,10 @@ pub struct Channel<C: ChannelPins> {
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/// for `i_set`
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pub dac: ad5680::Dac<C::DacSpi, C::DacSync>,
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pub shdn: C::Shdn,
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/// stm32f4 integrated adc
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pub adc: C::Adc,
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pub itec_pin: C::ItecPin,
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/// feedback from `dac` output
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pub dac_loopback: C::DacLoopback,
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pub dac_loopback_pin: C::DacLoopbackPin,
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}
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@ -29,7 +31,8 @@ impl<C: ChannelPins> Channel<C> {
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state,
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dac,
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shdn: pins.shdn,
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dac_loopback: pins.dac_loopback,
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adc: pins.adc,
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itec_pin: pins.itec_pin,
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dac_loopback_pin: pins.dac_loopback_pin,
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}
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}
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@ -84,15 +84,29 @@ impl Channels {
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pub fn read_dac_loopback(&mut self, channel: usize) -> u16 {
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match channel {
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0 => self.channel0.dac_loopback.convert(
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0 => self.channel0.adc.convert(
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&self.channel0.dac_loopback_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480
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),
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1 => self.channel1.dac_loopback.convert(
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1 => self.channel1.adc.convert(
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&self.channel1.dac_loopback_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480
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),
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_ => unreachable!(),
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}
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}
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pub fn read_itec(&mut self, channel: usize) -> u16 {
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match channel {
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0 => self.channel0.adc.convert(
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&self.channel0.itec_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480
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),
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1 => self.channel1.adc.convert(
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&self.channel1.itec_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480
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),
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_ => unreachable!(),
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}
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}
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}
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11
src/main.rs
11
src/main.rs
@ -142,11 +142,18 @@ fn main() -> ! {
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for channel in 0..CHANNELS {
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if let Some(adc_data) = channels.channel_state(channel).adc_data {
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let dac_loopback = channels.read_dac_loopback(channel);
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let itec = channels.read_itec(channel);
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let dcc_u = 5.0;
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let itec_u = dcc_u * (itec as f64) / (0xFFF as f64);
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let tec_u = (itec_u - 1.5) / 8.0;
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let tec_r = 5.0;
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let tec_i = tec_u / tec_r;
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let state = channels.channel_state(channel);
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let _ = writeln!(
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socket, "t={} raw{}=0x{:06X} dac_loopback=0x{:X}",
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socket, "t={} raw{}=0x{:06X} dac_loopback=0x{:X} itec=0x{:X} tec={:.2}V/{:.2}A",
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state.adc_time, channel, adc_data,
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dac_loopback
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dac_loopback, itec,
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tec_u, tec_i,
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);
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}
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}
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28
src/pins.rs
28
src/pins.rs
@ -26,7 +26,8 @@ pub trait ChannelPins {
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type DacSpi: Transfer<u8>;
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type DacSync: OutputPin;
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type Shdn: OutputPin;
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type DacLoopback;
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type Adc;
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type ItecPin;
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type DacLoopbackPin;
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}
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@ -34,7 +35,8 @@ impl ChannelPins for Channel0 {
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type DacSpi = Dac0Spi;
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type DacSync = PE4<Output<PushPull>>;
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type Shdn = PE10<Output<PushPull>>;
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type DacLoopback = Adc<ADC1>;
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type Adc = Adc<ADC1>;
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type ItecPin = PA6<Analog>;
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type DacLoopbackPin = PA4<Analog>;
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}
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@ -42,7 +44,8 @@ impl ChannelPins for Channel1 {
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type DacSpi = Dac1Spi;
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type DacSync = PF6<Output<PushPull>>;
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type Shdn = PE15<Output<PushPull>>;
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type DacLoopback = Adc<ADC2>;
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type Adc = Adc<ADC2>;
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type ItecPin = PB0<Analog>;
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type DacLoopbackPin = PA5<Analog>;
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}
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@ -57,7 +60,8 @@ pub struct ChannelPinSet<C: ChannelPins> {
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pub dac_spi: C::DacSpi,
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pub dac_sync: C::DacSync,
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pub shdn: C::Shdn,
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pub dac_loopback: C::DacLoopback,
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pub adc: C::Adc,
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pub itec_pin: C::ItecPin,
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pub dac_loopback_pin: C::DacLoopbackPin,
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}
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@ -106,14 +110,16 @@ impl Pins {
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);
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let mut shdn0 = gpioe.pe10.into_push_pull_output();
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let _ = shdn0.set_low();
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let mut dac_loopback0 = Adc::adc1(adc1, true, Default::default());
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dac_loopback0.enable();
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let mut adc0 = Adc::adc1(adc1, true, Default::default());
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adc0.enable();
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let itec0_pin = gpioa.pa6.into_analog();
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let dac_loopback0_pin = gpioa.pa4.into_analog();
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let channel0 = ChannelPinSet {
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dac_spi: dac0_spi,
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dac_sync: dac0_sync,
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shdn: shdn0,
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dac_loopback: dac_loopback0,
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adc: adc0,
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itec_pin: itec0_pin,
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dac_loopback_pin: dac_loopback0_pin,
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};
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@ -123,14 +129,16 @@ impl Pins {
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);
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let mut shdn1 = gpioe.pe15.into_push_pull_output();
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let _ = shdn1.set_low();
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let mut dac_loopback1 = Adc::adc2(adc2, true, Default::default());
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dac_loopback1.enable();
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let mut adc1 = Adc::adc2(adc2, true, Default::default());
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adc1.enable();
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let itec1_pin = gpiob.pb0.into_analog();
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let dac_loopback1_pin = gpioa.pa5.into_analog();
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let channel1 = ChannelPinSet {
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dac_spi: dac1_spi,
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dac_sync: dac1_sync,
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shdn: shdn1,
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dac_loopback: dac_loopback1,
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adc: adc1,
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itec_pin: itec1_pin,
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dac_loopback_pin: dac_loopback1_pin,
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};
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