ad7172: retry corrupt transfers
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parent
82dba2bb67
commit
4c3c8498e9
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@ -1,7 +1,7 @@
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use core::fmt;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use log::info;
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use log::{info, warn};
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use super::checksum::{ChecksumMode, Checksum};
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use super::AdcError;
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use super::{
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@ -145,12 +145,16 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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checksum.feed(&[address]);
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let checksum_out = checksum.result();
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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loop {
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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checksum.feed(®_data);
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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checksum.feed(®_data);
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let checksum_expected = checksum.result();
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if checksum_expected == checksum_in {
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break;
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}
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// Retry
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warn!("read_reg checksum error, retrying");
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}
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Ok(reg_data)
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}
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@ -166,7 +170,13 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
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checksum.feed(&[address]);
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checksum.feed(®_data);
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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loop {
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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if checksum_in.unwrap_or(0) == 0 {
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break;
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}
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warn!("write_reg: checksum={:02X}, retrying", checksum_in.unwrap_or(0));
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}
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Ok(())
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}
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