diff --git a/src/ad7172/adc.rs b/src/ad7172/adc.rs
index 24438b5..e3289e7 100644
--- a/src/ad7172/adc.rs
+++ b/src/ad7172/adc.rs
@@ -134,12 +134,12 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
         let mut reg_data = R::Data::empty();
         let address = 0x40 | reg.address();
         let mut checksum = Checksum::new(self.checksum_mode);
-        checksum.feed(address);
+        checksum.feed(&[address]);
         let checksum_out = checksum.result();
+
         let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
-        for &mut b in reg_data.as_mut() {
-            checksum.feed(b);
-        }
+
+        checksum.feed(&reg_data);
         let checksum_expected = checksum.result();
         if checksum_expected != checksum_in {
             return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
@@ -155,10 +155,8 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
             ChecksumMode::Xor => ChecksumMode::Crc,
             ChecksumMode::Crc => ChecksumMode::Crc,
         });
-        checksum.feed(address);
-        for &mut b in reg_data.as_mut() {
-            checksum.feed(b);
-        }
+        checksum.feed(&[address]);
+        checksum.feed(&reg_data);
         let checksum_out = checksum.result();
         self.transfer(address, reg_data.as_mut(), checksum_out)?;
         Ok(())
diff --git a/src/ad7172/checksum.rs b/src/ad7172/checksum.rs
index 3c93171..496eb7c 100644
--- a/src/ad7172/checksum.rs
+++ b/src/ad7172/checksum.rs
@@ -27,7 +27,7 @@ impl Checksum {
         Checksum { mode, state: 0 }
     }
 
-    pub fn feed(&mut self, input: u8) {
+    fn feed_byte(&mut self, input: u8) {
         match self.mode {
             ChecksumMode::Off => {},
             ChecksumMode::Xor => self.state ^= input,
@@ -45,6 +45,12 @@ impl Checksum {
         }
     }
 
+    pub fn feed(&mut self, input: &[u8]) {
+        for &b in input {
+            self.feed_byte(b);
+        }
+    }
+
     pub fn result(&self) -> Option<u8> {
         match self.mode {
             ChecksumMode::Off => None,
diff --git a/src/ad7172/regs.rs b/src/ad7172/regs.rs
index e96a066..52c7b87 100644
--- a/src/ad7172/regs.rs
+++ b/src/ad7172/regs.rs
@@ -1,3 +1,4 @@
+use core::ops::{Deref, DerefMut};
 use byteorder::{BigEndian, ByteOrder};
 use bit_field::BitField;
 
@@ -7,9 +8,8 @@ pub trait Register {
     type Data: RegisterData;
     fn address(&self) -> u8;
 }
-pub trait RegisterData {
+pub trait RegisterData: Deref<Target=[u8]> + DerefMut {
     fn empty() -> Self;
-    fn as_mut(&mut self) -> &mut [u8];
 }
 
 macro_rules! def_reg {
@@ -32,8 +32,15 @@ macro_rules! def_reg {
                 fn empty() -> Self {
                     Data([0; $size])
                 }
-                /// Borrow for SPI transfer
-                fn as_mut(&mut self) -> &mut [u8] {
+            }
+            impl core::ops::Deref for Data {
+                type Target = [u8];
+                fn deref(&self) -> &[u8] {
+                    &self.0
+                }
+            }
+            impl core::ops::DerefMut for Data {
+                fn deref_mut(&mut self) -> &mut [u8] {
                     &mut self.0
                 }
             }
@@ -53,7 +60,15 @@ macro_rules! def_reg {
                 fn empty() -> Self {
                     Data([0; $size])
                 }
-                fn as_mut(&mut self) -> &mut [u8] {
+            }
+            impl core::ops::Deref for Data {
+                type Target = [u8];
+                fn deref(&self) -> &[u8] {
+                    &self.0
+                }
+            }
+            impl core::ops::DerefMut for Data {
+                fn deref_mut(&mut self) -> &mut [u8] {
                     &mut self.0
                 }
             }