2020-03-13 04:27:03 +08:00
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use stm32f4xx_hal::{
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2020-03-21 07:22:38 +08:00
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hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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},
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2020-03-13 04:27:03 +08:00
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time::MegaHertz,
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spi,
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};
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2020-05-29 02:45:42 +08:00
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use crate::timer::sleep;
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2020-03-13 04:27:03 +08:00
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2020-05-14 05:19:09 +08:00
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/// SPI Mode 1
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2020-03-13 04:27:03 +08:00
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pub const SPI_MODE: spi::Mode = spi::Mode {
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2020-05-14 05:19:09 +08:00
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polarity: spi::Polarity::IdleLow,
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phase: spi::Phase::CaptureOnSecondTransition,
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2020-03-13 04:27:03 +08:00
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};
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/// 30 MHz
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pub const SPI_CLOCK: MegaHertz = MegaHertz(30);
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2020-05-14 05:19:20 +08:00
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pub const MAX_VALUE: u32 = 0x3FFFF;
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2020-03-20 01:34:57 +08:00
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2020-03-13 04:27:03 +08:00
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/// [AD5680](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5680.pdf) DAC
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pub struct Dac<SPI: Transfer<u8>, S: OutputPin> {
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spi: SPI,
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sync: S,
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}
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impl<SPI: Transfer<u8>, S: OutputPin> Dac<SPI, S> {
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pub fn new(spi: SPI, mut sync: S) -> Self {
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2020-05-16 07:18:14 +08:00
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let _ = sync.set_low();
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2020-03-13 04:27:03 +08:00
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Dac {
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spi,
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sync,
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}
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}
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2020-05-29 02:45:42 +08:00
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fn write(&mut self, buf: &mut [u8]) -> Result<(), SPI::Error> {
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2020-05-16 07:18:14 +08:00
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// pulse sync to start a new transfer. leave sync idle low
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// afterwards to save power as recommended per datasheet.
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2020-03-13 04:27:03 +08:00
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let _ = self.sync.set_high();
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2020-05-29 02:45:42 +08:00
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// must be high for >= 33 ns
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sleep(1);
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2020-05-16 07:18:14 +08:00
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let _ = self.sync.set_low();
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2020-05-29 02:45:42 +08:00
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self.spi.transfer(buf)?;
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2020-05-16 07:18:14 +08:00
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Ok(())
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2020-03-13 04:27:03 +08:00
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}
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2020-09-17 04:05:31 +08:00
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pub fn set(&mut self, value: u32) -> Result<u32, SPI::Error> {
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2020-09-07 01:06:31 +08:00
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let value = value.min(MAX_VALUE);
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2020-05-29 02:45:42 +08:00
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let mut buf = [
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2020-03-13 04:27:03 +08:00
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(value >> 14) as u8,
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(value >> 6) as u8,
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(value << 2) as u8,
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];
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2020-09-17 04:05:31 +08:00
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self.write(&mut buf)?;
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Ok(value)
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2020-03-13 04:27:03 +08:00
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}
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}
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