2020-05-21 05:07:31 +08:00
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use stm32f4xx_hal::hal::digital::v2::OutputPin;
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2020-05-17 07:23:35 +08:00
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use crate::{
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ad5680,
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2020-09-14 05:15:48 +08:00
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ad7172,
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2020-05-17 07:23:35 +08:00
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channel_state::ChannelState,
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pins::{ChannelPins, ChannelPinSet},
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};
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2020-05-13 05:16:57 +08:00
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/// Marker type for the first channel
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pub struct Channel0;
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/// Marker type for the second channel
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pub struct Channel1;
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pub struct Channel<C: ChannelPins> {
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pub state: ChannelState,
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2020-05-17 01:36:00 +08:00
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/// for `i_set`
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2020-05-13 05:16:57 +08:00
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pub dac: ad5680::Dac<C::DacSpi, C::DacSync>,
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2020-05-19 06:15:39 +08:00
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/// 1 / Volts
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pub dac_factor: f64,
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2020-05-13 05:16:57 +08:00
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pub shdn: C::Shdn,
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2020-05-19 04:43:44 +08:00
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pub vref_pin: C::VRefPin,
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2020-05-17 05:59:31 +08:00
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pub itec_pin: C::ItecPin,
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2020-05-17 01:36:00 +08:00
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/// feedback from `dac` output
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2020-05-17 08:18:25 +08:00
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pub dac_feedback_pin: C::DacFeedbackPin,
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2020-05-19 03:38:13 +08:00
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pub tec_u_meas_pin: C::TecUMeasPin,
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2020-05-13 05:16:57 +08:00
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}
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impl<C: ChannelPins> Channel<C> {
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2020-09-14 05:15:48 +08:00
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pub fn new(mut pins: ChannelPinSet<C>, adc_calibration: ad7172::ChannelCalibration) -> Self {
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let state = ChannelState::new(adc_calibration);
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2020-05-13 05:16:57 +08:00
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let mut dac = ad5680::Dac::new(pins.dac_spi, pins.dac_sync);
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2020-05-19 06:15:39 +08:00
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let _ = dac.set(0);
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2020-05-21 05:07:03 +08:00
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// power up TEC
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let _ = pins.shdn.set_high();
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2020-05-19 06:15:39 +08:00
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// sensible dummy preset. calibrate_i_set() must be used.
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let dac_factor = ad5680::MAX_VALUE as f64 / 5.0;
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2020-05-13 05:16:57 +08:00
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Channel {
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state,
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2020-05-19 06:15:39 +08:00
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dac, dac_factor,
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2020-05-13 05:16:57 +08:00
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shdn: pins.shdn,
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2020-05-19 04:43:44 +08:00
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vref_pin: pins.vref_pin,
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2020-05-17 05:59:31 +08:00
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itec_pin: pins.itec_pin,
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2020-05-17 08:18:25 +08:00
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dac_feedback_pin: pins.dac_feedback_pin,
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2020-05-19 03:38:13 +08:00
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tec_u_meas_pin: pins.tec_u_meas_pin,
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2020-05-13 05:16:57 +08:00
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}
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}
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}
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