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add apmaster, apsatellite{1,2}

pull/2/head
Harry Ho 7 months ago
parent
commit
db9883f360
  1. 47
      apmaster.json
  2. 66
      apsatellite1.json
  3. 59
      apsatellite2.json

47
apmaster.json

@ -0,0 +1,47 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "apmaster",
"hw_rev": "v1.1",
"base": "master",
"core_addr": "192.168.1.75",
"enable_sata_drtio": true,
"peripherals": [
{
"type": "urukul",
"dds": "ad9912",
"ports": [1, 2],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [3, 4],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [5, 6],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [7, 8],
"clk_sel": 2
},
{
"type": "dio",
"ports": [9],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [10],
"bank_direction_low": "output",
"bank_direction_high": "output"
}
]
}

66
apsatellite1.json

@ -0,0 +1,66 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "apsatellite1",
"hw_rev": "v1.1",
"base": "satellite",
"enable_sata_drtio": true,
"peripherals": [
{
"type": "dio",
"ports": [0],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [4, 5],
"clk_sel": 2
},
{
"type": "dio",
"ports": [6],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "mirny",
"ports": [7],
"clk_sel": "mmcx",
"refclk": 125e6
},
{
"type": "grabber",
"ports": [8, 9]
},
{
"type": "fastino",
"ports": [10]
},
{
"type": "dio",
"ports": [11],
"bank_direction_low": "output",
"bank_direction_high": "output"
}
]
}

59
apsatellite2.json

@ -0,0 +1,59 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "apsatellite2",
"hw_rev": "v2.0",
"base": "satellite",
"peripherals": [
{
"type": "sampler",
"ports": [0]
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [1, 2],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [3],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [4],
"clk_sel": 2
},
{
"type": "sampler",
"ports": [5]
},
{
"type": "dio",
"ports": [8],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [9],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [10],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [11],
"bank_direction_low": "output",
"bank_direction_high": "output"
}
]
}
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