From fc1a7728f16dc80e3ff231f4a4daa3dd73751e8d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Tue, 18 Aug 2020 17:16:13 +0200
Subject: [PATCH] luh, qleds: update

---
 luh.json   | 35 ++++++++++++++++++++---------------
 qleds.json | 16 +++++++++++-----
 2 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/luh.json b/luh.json
index 5f50eaa..dbd789f 100644
--- a/luh.json
+++ b/luh.json
@@ -17,37 +17,42 @@
             "bank_direction_low": "output",
             "bank_direction_high": "output"
         },
-        {
-            "type": "dio",
-            "ports": [2],
-            "bank_direction_low": "output",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "sampler",
-            "ports": [3]
-        },
         {
             "type": "urukul",
-            "ports": [4],
+            "ports": [3, 2],
             "clk_sel": 0,
             "refclk": 100e6,
             "pll_n": 40
         },
         {
             "type": "urukul",
-            "ports": [5],
+            "ports": [5, 4],
+            "clk_sel": 0,
+            "refclk": 100e6,
+            "pll_n": 40
+        },
+        {
+            "type": "urukul",
+            "ports": [7, 6],
             "clk_sel": 0,
             "refclk": 100e6,
             "pll_n": 40
         },
         {
             "type": "grabber",
-            "ports": [6]
+            "ports": [8]
         },
         {
-            "type": "zotino",
-            "ports": [7]
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "fastino",
+            "ports": [10]
+        },
+        {
+            "type": "fastino",
+            "ports": [11]
         }
    ]
 }
diff --git a/qleds.json b/qleds.json
index cdd72ce..4da1f3d 100644
--- a/qleds.json
+++ b/qleds.json
@@ -25,30 +25,36 @@
             "bank_direction_high": "output"
         },
         {
-            "type": "sampler",
-            "ports": [3]
+            "type": "dio",
+            "ports": [3],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
         },
         {
             "type": "urukul",
-            "ports": [6, 5],
+            "ports": [5, 4],
             "clk_sel": 0,
             "refclk": 100e6,
             "pll_n": 40
         },
         {
             "type": "urukul",
-            "ports": [8, 7],
+            "ports": [7, 6],
             "clk_sel": 0,
             "refclk": 100e6,
             "pll_n": 40
         },
         {
             "type": "urukul",
-            "ports": [10, 9],
+            "ports": [9, 8],
             "clk_sel": 0,
             "refclk": 100e6,
             "pll_n": 40
         },
+        {
+            "type": "zotino",
+            "ports": [10]
+        },
         {
             "type": "zotino",
             "ports": [11]