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sinara-systems-legacy
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add eindhoven

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SingularitySurfer 2022-06-08 14:09:18 +00:00
parent 99eee60a5e
commit f0590424af
1 changed files with 74 additions and 0 deletions
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{
"_description": "Technise Universiteit Eindhoven, M. Lomidze/E. Vredenbregt",
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "eindhoven",
"hw_rev": "v2.0",
"ext_ref_frequency": 10e6,
"base": "standalone",
"core_addr": "10.34.16.100",
"vendor": "QUARTIQ",
"peripherals": [
{
"type": "dio",
"board": "DIO_MCX",
"ports": [0],
"hw_rev": "v1.0",
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_MCX",
"ports": [1],
"hw_rev": "v1.0",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_MCX",
"ports": [2],
"hw_rev": "v1.0",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_MCX",
"ports": [3],
"hw_rev": "v1.0",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "urukul",
"hw_rev": "v1.5",
"ports": [4, 5],
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"hw_rev": "v1.5",
"ports": [6, 7],
"clk_sel": 2,
"synchronization": true
},
{
"type": "grabber",
"hw_rev": "v1.1",
"ports": [10]
},
{
"type": "sampler",
"hw_rev": "v2.2",
"ports": [11, 8]
},
{
"type": "fastino",
"hw_rev": "v1.2",
"ports": [9]
}
]
}