add old version of the sias system

master
ciciwu 2021-12-23 17:03:26 +08:00
parent 1e1a956121
commit d153d9c9e2
2 changed files with 62 additions and 23 deletions

50
sias2.json Normal file
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@ -0,0 +1,50 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "sias2",
"hw_rev": "v2.0",
"base": "standalone",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "dio",
"board": "DIO_SMA",
"ports": [0],
"edge_counter": true,
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "fastino",
"ports": [4]
},
{
"type": "suservo",
"sampler_ports": [10, 11],
"urukul0_ports": [6, 7],
"urukul1_ports": [8, 9],
"clk_sel": 2
}
]
}

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@ -7,43 +7,32 @@
"peripherals": [ "peripherals": [
{ {
"type": "dio", "type": "dio",
"board": "DIO_SMA",
"ports": [0], "ports": [0],
"edge_counter": true,
"bank_direction_low": "input", "bank_direction_low": "input",
"bank_direction_high": "output" "bank_direction_high": "output"
}, },
{ {
"type": "dio", "type": "dio",
"board": "DIO_SMA",
"ports": [1], "ports": [1],
"bank_direction_low": "output", "bank_direction_low": "output",
"bank_direction_high": "output" "bank_direction_high": "output"
}, },
{ {
"type": "dio", "type": "suservo",
"board": "DIO_SMA", "sampler_ports": [2, 3],
"ports": [2], "urukul0_ports": [4, 5],
"bank_direction_low": "output", "urukul1_ports": [6, 7],
"bank_direction_high": "output" "clk_sel": 2
}, },
{ {
"type": "dio", "type": "urukul",
"board": "DIO_SMA", "dds": "ad9910",
"ports": [3], "ports": [8, 9],
"bank_direction_low": "output", "clk_sel": 2
"bank_direction_high": "output"
}, },
{ {
"type": "fastino", "type": "fastino",
"ports": [4] "ports": [10]
},
{
"type": "suservo",
"sampler_ports": [10, 11],
"urukul0_ports": [6, 7],
"urukul1_ports": [8, 9],
"clk_sel": 2
} }
] ]
} }