From bfbe99491c767e7091c434de521657e6ff87f90a Mon Sep 17 00:00:00 2001 From: SingularitySurfer Date: Thu, 30 Dec 2021 09:16:15 +0000 Subject: [PATCH] add luh4 and ptb11 --- luh4.json | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ ptb11.json | 41 ++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 luh4.json create mode 100644 ptb11.json diff --git a/luh4.json b/luh4.json new file mode 100644 index 0000000..9ed8145 --- /dev/null +++ b/luh4.json @@ -0,0 +1,61 @@ +{ + "_description": "LUH Barbay", + "target": "kasli", + "min_artiq_version": "6.0", + "variant": "luh4", + "hw_rev": "v2.0", + "ext_ref_frequency": 10e6, + "base": "standalone", + "core_addr": "10.34.16.100", + "vendor": "QUARTIQ", + "peripherals": [ + { + "type": "dio", + "board": "DIO_BNC", + "ports": [0], + "hw_rev": "v1.4", + "bank_direction_low": "input", + "bank_direction_high": "output" + }, + { + "type": "dio", + "board": "DIO_RJ45", + "hw_rev": "v1.2", + "ports": [1], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "dio", + "board": "DIO_RJ45", + "hw_rev": "v1.2", + "ports": [2], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "urukul", + "hw_rev": "v1.5", + "ports": [3,4], + "clk_sel": 2, + "synchronization": true + }, + { + "type": "urukul", + "hw_rev": "v1.5", + "ports": [5,6], + "clk_sel": 2, + "synchronization": true + }, + { + "type": "sampler", + "hw_rev": "v2.2", + "ports": [7,10] + }, + { + "type": "fastino", + "hw_rev": "v1.2", + "ports": [8] + } + ] +} diff --git a/ptb11.json b/ptb11.json new file mode 100644 index 0000000..a6d05b6 --- /dev/null +++ b/ptb11.json @@ -0,0 +1,41 @@ +{ + "_description": "PTB Spieß", + "target": "kasli", + "min_artiq_version": "6.0", + "variant": "ptb11", + "hw_rev": "v2.0", + "ext_ref_frequency": 10e6, + "base": "standalone", + "core_addr": "10.34.16.100", + "vendor": "QUARTIQ", + "peripherals": [ + { + "type": "dio", + "board": "DIO_SMA", + "ports": [0], + "hw_rev": "v1.2", + "bank_direction_low": "input", + "bank_direction_high": "output" + }, + { + "type": "urukul", + "hw_rev": "v1.5", + "ports": [1,2], + "clk_sel": 2, + "synchronization": true + }, + { + "type": "urukul", + "hw_rev": "v1.5", + "ports": [3,4], + "clk_sel": 2, + "synchronization": true + }, + { + "type": "sampler", + "hw_rev": "v2.2", + "ports": [5,6] + } + + ] +}