Browse Source

add tsinghua3

master
Sebastien Bourdeauducq 5 months ago
parent
commit
bcceaec71e
  1. 69
      tsinghua3.json

69
tsinghua3.json

@ -0,0 +1,69 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "tsinghua3",
"hw_rev": "v2.0",
"ext_ref_frequency": 10e6,
"base": "master",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "grabber",
"ports": [0, 1]
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [4],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [5],
"bank_direction_low": "output",
"bank_direction_high": "input"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [6],
"edge_counter": true,
"bank_direction_low": "input",
"bank_direction_high": "input"
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [7, 8],
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [9, 10],
"clk_sel": 2,
"synchronization": true
},
{
"type": "zotino",
"ports": [11]
}
]
}
Loading…
Cancel
Save